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da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 1 of 183 ? 2016 dialog semiconductor general d escription the da9053 is a quad buck 1 a per channel pmic subsystem with supply domain flexibility to support a wide range of application processors, associated peripherals and user interface functions. combining a dual input switched - mode usb compatible charger, full power path management , four bucks, ten linear regulators and support for multiple sleep modes : the da9053 offers an energy - optimized solution suitable for portable handheld, wireless , industrial and infotainment applications. the high - efficiency li - lon/polymer switching charger supports precise current/voltage charging as well as pre - charge and usb modes without processor int eraction. during charging, the die temperature is thermally regulated enabling high - capacity batteries to be rapidl y charged at currents up to 1.8 a with minimum thermal impact. usb suspend mode operation is supported and, for robustness, the power inputs are protected against over - voltage conditions. the autonomous power - path controller seamlessly detects and manages energy flow between an ac adaptor, usb cable, and battery while maintaining usb power specification compliance. the internally - generated sys tem power rail supports power scenarios such as instant - on with a fully discharged battery. a reverse - protected backup battery charger is also integrated into the powerpath function. controlled by a programmable digital power manager, the 14 user - programm able switched/linear regulators can be configured to meet the start - up sequence, voltage, and timing requirements for most applications. the power manager includes supply - rail qualification and system reset management. for optimal processor energy - per - task performance, dynamic voltage scaling (dvs) is available on up to five supply domains. dialogs patented smartmirror? dynamic biasing is implemented on all linear regulators. an integrated 10 - channel general purpose adc includes support for a touch screen controller with pen down detect, programmable high and low thresholds, an integrated current source for resistive measurements, and system voltage monitoring with a programmable low - voltage warning. the adc has 8 - bit resolution in auto - mode and 10 - bit res olution in manual conversion mode. key f eatures switched dc/usb c harger with power path management four b uck c onverters ( three have dvs) 0.5 v to 2.5 v up to 2 a ten p rogrammable ldos , high psrr, 1 % accuracy low - power b ackup c harger , 1.1 v to 3.1 v , up to 6 ma 32 khz r eal time cl ock (rtc) with alarm wake - up ten channel g eneral p urpose adc with touch screen interface high - voltage white led driver b oost, three strings sixteen flexible gpio pins for enhanced wakeup and peripheral control 2 - wire and 4 - wi re control , 2 - wire and 4 - wire control interfaces system watchdog function - 40 c to +125 c junction temperature operation 7x7x1 mm 0.5 mm pitch and 11x11x1 mm 0. 8 mm pitch vfbga package options aec q100 grade 3 option typical applications mobile internet devices and t ablet pcs iot devices personal n avigation d evices consumer and in - vehicle i nfotainment d evices
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 2 of 183 ? 2016 dialog semiconductor contents general description ................................ ................................ ................................ ............................ 1 key features ................................ ................................ ................................ ................................ ........ 1 typical applications ................................ ................................ ................................ ............................ 1 contents ................................ ................................ ................................ ................................ ............... 2 figures ................................ ................................ ................................ ................................ .................. 6 1 terms and definitions ................................ ................................ ................................ ................... 9 2 block diagram ................................ ................................ ................................ ............................. 10 3 generated supply domains ................................ ................................ ................................ ....... 11 4 pad description ................................ ................................ ................................ ........................... 13 5 electrical characteristics ................................ ................................ ................................ ........... 18 5.1 absolute maximum ratings ................................ ................................ ................................ 18 5.2 recommended operating conditions ................................ ................................ ................. 19 5.3 current consumption ................................ ................................ ................................ .......... 19 5.4 digital i/o characteristics ................................ ................................ ................................ .... 20 5.5 gpio characteristics ................................ ................................ ................................ .......... 21 5.6 power on reset ................................ ................................ ................................ ................... 21 5.7 watchd og ................................ ................................ ................................ ............................ 22 5.8 power manager and hs - 2 - wire control bus ................................ ................................ ...... 22 5.9 4 - wire control bus timing ................................ ................................ ................................ .. 23 5.10 oscillator ................................ ................................ ................................ ............................. 24 5.11 referen ce voltage generation and temperature supervision ................................ ........... 24 5.12 ldo voltage regulators ................................ ................................ ................................ ..... 24 5.12.1 ldo1 ................................ ................................ ................................ .................... 24 5.12.2 ldo2 ................................ ................................ ................................ .................... 26 5.12.3 ldo3 ................................ ................................ ................................ .................... 27 5.12.4 ldo4 ................................ ................................ ................................ .................... 28 5.12.5 ldo5 ................................ ................................ ................................ .................... 29 5.12.6 ldo6 ................................ ................................ ................................ .................... 30 5.12.7 ldo7 ................................ ................................ ................................ .................... 31 5.12.8 ldo8 ................................ ................................ ................................ .................... 32 5.12.9 ldo9 ................................ ................................ ................................ .................... 33 5.12.10 ldo10 ................................ ................................ ................................ .................. 34 5.12.11 ldocore ................................ ................................ ................................ ........... 35 5.13 dc/dc b uck converters ................................ ................................ ................................ ..... 35 5.13.1 buckcore ................................ ................................ ................................ ........ 35 5.13.2 buckpro ................................ ................................ ................................ ........... 37 5.13.3 buckmem ................................ ................................ ................................ .......... 39 5.13.4 buckperi ................................ ................................ ................................ .......... 40 5.14 battery charger ................................ ................................ ................................ ................... 43
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 3 of 183 ? 2016 dialog semiconductor 5.14.1 charger supply modes ................................ ................................ ........................ 43 5.14.2 charger buck ................................ ................................ ................................ ....... 43 5.14.3 voltage levels on vbat ................................ ................................ ...................... 44 5.14.4 charging modes ................................ ................................ ................................ .. 45 5.14.5 charger detection circuit ................................ ................................ .................... 45 5.14.6 vbus charge control ................................ ................................ .......................... 45 5.14.7 charge timer ................................ ................................ ................................ ....... 46 5.14.8 d ccc and active - diode ................................ ................................ ...................... 46 5.14.9 backup battery charger ................................ ................................ ...................... 46 5.14.10 boost converter ................................ ................................ ................................ ... 47 5.14.11 wled driver ................................ ................................ ................................ ........ 48 5.15 adc ................................ ................................ ................................ ................................ ..... 48 6 accessory iden tity detection (acc_id_det) ................................ ................................ ........... 50 6.1 accessory detection states ................................ ................................ ................................ 50 6.2 32 khz oscillator ................................ ................................ ................................ ................. 51 6.3 rt c counter and alarm ................................ ................................ ................................ ...... 51 6.4 oscillator ................................ ................................ ................................ ............................. 52 7 id code/scratch pad ................................ ................................ ................................ ................... 53 7.1 programming the id code/scratch pad ................................ ................................ .............. 53 8 typical characteristics ................................ ................................ ................................ ............... 54 8.1 buck regulator performance ................................ ................................ .............................. 54 8.2 linear regulator performance ................................ ................................ ............................ 55 8.3 typical ldo voltage vs temperature ................................ ................................ ................. 56 8.4 adc performance ................................ ................................ ................................ ............... 56 8.5 power path performance ................................ ................................ ................................ .... 57 8.6 boost and led current control performance ................................ ................................ ..... 58 9 functional description ................................ ................................ ................................ ............... 59 9.1 power manager io ports ................................ ................................ ................................ ..... 59 9.2 on/off and hw - watchdog port (nonkey/keep_act) ................................ .................... 59 9.3 hardware reset (nshutdown, nonkey, gpio14 & gpio15) ................................ ...... 59 9.4 reset output (nreset) ................................ ................................ ................................ ...... 60 9.5 accessory and id detect (acc_id_det) ................................ ................................ ........... 60 9.6 system enable (sys_en) ................................ ................................ ................................ .. 60 9.7 power enable (pwr_en) ................................ ................................ ................................ ... 60 9. 8 power1 enable (pwr1_en) ................................ ................................ ............................... 60 9.9 general purpose feedback signal 1 (gp_fb1: ext_wakeup/ready) ........................ 61 9.10 power domain status (sys_up, pwr_up/gp_fb2) ................................ ....................... 61 9.11 supply rail fault (nvdd_fault) ................................ ................................ ...................... 61 9.12 interrupt request (nirq) ................................ ................................ ................................ ..... 61 9.13 real time clock output (out_32k) ................................ ................................ .................. 61 9.14 io supply voltage (vdd_io1 and vdd_io2) ................................ ................................ ..... 61 10 control interfaces ................................ ................................ ................................ ........................ 62 10.1 power manager interface (4 - wire and 2 - wire control bus) ................................ ............... 62 10.2 4 - wire communication ................................ ................................ ................................ ........ 62
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 4 of 183 ? 2016 dialog semiconductor 10.3 2 - wire communication ................................ ................................ ................................ ........ 65 10.3.1 details of the 2 - wire control bus protocol ................................ .......................... 65 10.4 alternative high speed 2 - wire interface ................................ ................................ ............. 67 11 operating modes ................................ ................................ ................................ ......................... 68 11.1 active mode ................................ ................................ ................................ ..................... 68 11.2 power - d own mode ................................ ................................ ................................ ........ 68 11.3 reset mode ................................ ................................ ................................ ...................... 68 11.4 no - power mode ................................ ................................ ................................ .............. 69 11.5 power commander mode ................................ ................................ ................................ ... 69 11 .6 start - up from no - power mode ................................ ................................ ....................... 71 11.6.1 power - on - reset (npor) ................................ ................................ ..................... 71 11.7 application wake - up ................................ ................................ ................................ ........... 72 11.8 system monitor (watchdog) ................................ ................................ ............................... 72 11.9 wake - up events ................................ ................................ ................................ ................. 73 12 register page control ................................ ................................ ................................ ................. 79 12.1 power manager control and monitoring ................................ ................................ ............. 79 13 gpio extender ................................ ................................ ................................ ............................. 90 14 power sup ply sequencer ................................ ................................ ................................ ........... 98 15 voltage regulators ................................ ................................ ................................ .................... 104 15.1 core regulator ldocore ................................ ................................ ............................... 105 15.2 dc/dc buck converters ................................ ................................ ................................ ... 105 15.3 converters buckcore, buckpro and buckmem with dvc ................................ ..... 106 16 power supplies ................................ ................................ ................................ .......................... 108 17 program mable battery charger ................................ ................................ ............................... 127 17.1 high efficiency charger dc - dc buck converter ................................ .............................. 127 17.2 charger supply detection/vbus monitoring ................................ ................................ .... 127 17.3 vbus over - voltage protection and usb suspend ................................ .......................... 128 17.4 battery pre - charge mode ................................ ................................ ................................ . 128 17.5 fast linear - charge mode ................................ ................................ ................................ . 129 17.6 thermal charge current control ................................ ................................ ...................... 129 17.7 dynamic charging current control (dccc) and active - diode ................................ ........ 130 17.8 programmable charge termination by time ................................ ................................ .... 130 17.9 backup battery charger / battery switch ................................ ................................ .......... 130 17.10 battery charger ................................ ................................ ................................ ................. 131 17.11 backup battery charger ................................ ................................ ................................ .... 136 17.12 white led driver and boost converter ................................ ................................ ............ 137 17.13 boost and led driver ................................ ................................ ................................ ....... 138 18 monitoring adc and touch screen interface ................................ ................................ ......... 143 18.1 adc overview ................................ ................................ ................................ ................... 143 18.2 input mux ................................ ................................ ................................ ......................... 143 18.3 adc ................................ ................................ ................................ ................................ ... 143 18.4 manual conversion mode ................................ ................................ ................................ . 144 18.5 automatic measurements scheduler ................................ ................................ ................ 144 18.6 a0: vddout low voltage nirq measurement mode ................................ ..................... 144
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 5 of 183 ? 2016 dialog semiconductor 18.7 a1: ich (and ich_bat average) measurement mode ................................ .................... 145 18.8 a2: tbat and battery temperature warning nirq measurement mode ........................ 145 18.9 a4, a5, a6: automatic measurement and high/low threshold warning nirq mode ..... 145 18.10 a8: automatic measurement of internal temperature ................................ ...................... 145 18.11 a3, a9: manual measurement vbat and vbbat ................................ ............................ 145 18.12 fixed threshold non - adc warning nirq mode ................................ .............................. 146 18.13 a7: xy touch screen interface ................................ ................................ ........................ 146 18.13.1 features ................................ ................................ ................................ ............. 146 18.14 pen down detect ................................ ................................ ................................ .............. 146 18.15 tsi scheduler ................................ ................................ ................................ ................... 147 18.16 pen pressure ................................ ................................ ................................ .................... 148 18.17 gp - adc ................................ ................................ ................................ ............................ 149 19 tsi control ................................ ................................ ................................ ................................ . 154 20 rtc calendar and alarm ................................ ................................ ................................ .......... 157 21 register page 1 ................................ ................................ ................................ ......................... 160 22 customer otp ................................ ................................ ................................ ........................... 161 23 register map ................................ ................................ ................................ ............................. 164 23.1 overview ................................ ................................ ................................ ........................... 164 24 external component selection ................................ ................................ ................................ 169 24.1 capacitor selection ................................ ................................ ................................ ........... 169 24.2 inductor selection ................................ ................................ ................................ ............. 170 24.3 resistors ................................ ................................ ................................ ........................... 171 24.4 externa l pass transistors and schottky diodes ................................ ............................... 171 24.5 backup battery ................................ ................................ ................................ .................. 171 24.6 battery pack temperature sensor (ntc) ................................ ................................ ......... 172 24.7 crystal ................................ ................................ ................................ ............................... 172 25 layout guid elines ................................ ................................ ................................ ..................... 173 25.1 general recommendations ................................ ................................ .............................. 173 25.2 system supply and charger ................................ ................................ ............................. 173 25.3 ldos and switched mode supplies ................................ ................................ ................. 173 25.4 crystal oscillator ................................ ................................ ................................ ............... 174 25.5 thermal connection, land pad and stencil design ................................ ......................... 174 26 definitions ................................ ................................ ................................ ................................ .. 175 26.1 power dissipation and thermal design ................................ ................................ ............ 175 27 regulator parameters ................................ ................................ ................................ ............... 176 27.1 dropout voltage ................................ ................................ ................................ ................ 176 27.2 power supply rejection ................................ ................................ ................................ .... 176 27.3 line regulation ................................ ................................ ................................ ................. 176 27.4 load regulation ................................ ................................ ................................ ................ 177 28 dialog semiconductor 7x7 da9053 reference board bill of materials ............................... 178 28.1 dialog reference board component identification for bill of materials ............................ 178 29 package information ................................ ................................ ................................ ................. 180 29.1 package outlines ................................ ................................ ................................ .............. 180
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 6 of 183 ? 2016 dialog semiconductor 30 ordering information ................................ ................................ ................................ ................ 181 30.1 variants ordering information ................................ ................................ ........................... 181 revision history ................................ ................................ ................................ .............................. 182 figures figure 1: block diagram ................................ ................................ ................................ ...................... 10 figure 2: da9053 ballout (view from top, balls through package) ................................ ................. 13 figure 3: 2 - wire control bus timing diagram ................................ ................................ .................... 22 figure 4: 4 - wire control bus timing diagram ................................ ................................ .................... 23 figure 5: id detection circuitry ................................ ................................ ................................ ........... 50 figure 6: schematic of the rtc oscillator and counter functionality ................................ ................ 52 figure 7: buckperi efficiency curves ................................ ................................ .............................. 54 figure 8: buckcore efficiency curves ................................ ................................ ............................ 54 figure 9: buckpro efficiency curves ................................ ................................ ............................... 54 figure 10: buckmem efficiency curves ................................ ................................ ............................ 54 figure 11: buckpro load regulation transient ................................ ................................ .............. 54 figure 12: buckpro line regulation transient ................................ ................................ ............... 54 figure 13: typical ldo load regulation ................................ ................................ ............................ 55 figure 14: typical ldo drop - out voltage ................................ ................................ .......................... 55 figure 15: typical ldo line transient ................................ ................................ ................................ 55 figure 16: ldo load transient ................................ ................................ ................................ ........... 55 figure 17: typical ldo voltage vs temperature ................................ ................................ ................ 56 figure 18: adc dnl performance ................................ ................................ ................................ ...... 56 figure 19: adc inl performance ................................ ................................ ................................ ....... 56 figure 20: power path behaviour usb 100 mode ................................ ................................ .............. 57 figure 21: power path behaviour usb 500 mode ................................ ................................ .............. 57 figure 22: transitioning supply from vchg (via dcin) to vbat ................................ ....................... 57 figure 23: transit ioning supply from usb 5 v (via vbus) to vbat ................................ .................. 57 figure 24: wled current performance ................................ ................................ .............................. 58 figure 25: wled relative accuracy ................................ ................................ ................................ ... 58 figure 26: boost converter efficiency curves ................................ ................................ .................... 58 figure 27: boost regulation voltages ................................ ................................ ................................ . 58 figure 28: control ports and interface ................................ ................................ ................................ 59 figure 29: schematic of a 4 - wire and 2 - wire power manager bus ................................ ................... 62 figure 30: 4 - wire host write and read timing (ncs_pol = 0, cpol = 0, cpha = 0) ............... 63 figure 31: 4 - wire host write and read timing (ncs_pol = 0, cpol = 0, cpha = 1) ............... 63 figure 32: 4 - wire host write and read timing (ncs_pol = 0, cpol = 1, cpha = 0) ............... 64 figure 33: 4 - wire host write and read timing (ncs_pol = 0, cpol = 1, cpha = 1) ............... 64 figure 34: timing of 2 - wire start and stop condition ................................ ................................ .. 65 figure 35: 2 - wire byte write (so/data line) ................................ ................................ .................... 66 figure 36: examples of 2 - wire byte read (so/data line) ................................ ................................ 66 figure 37: examples of 2 - wire page read (so/data line) ................................ ............................... 66 figure 38: 2 - wire page write (so/data line) ................................ ................................ .................... 67 figure 39: 2 - wire repeated write (so/data line) ................................ ................................ ............. 67 figure 40: start - up from no - power to power - down mode ................................ ....................... 72 figure 41: content of otp power sequencer register cel l ................................ ............................... 74 figure 42: allocation of supplies (ids) to the sequencer time slots ................................ ................. 76 figure 43: typical power - up timing ................................ ................................ ................................ ... 98 figure 44: power mode transitions ................................ ................................ ................................ .... 99 figure 45: smart mirror tm voltage regulator ................................ ................................ .................... 104 figure 46: dcdc buck converter ................................ ................................ ................................ ..... 106 figure 47: buckperi / buckmem output switches ................................ ................................ ...... 107 figure 48: dccc and active diode operation ................................ ................................ .................. 130
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 7 of 183 ? 2016 dialog semiconductor figure 49: example of white led backlight application ................................ ................................ ... 137 figure 50: adc block diagram ................................ ................................ ................................ ......... 143 figure 51: example sequence of auto - adc measurements ................................ ......................... 144 figure 52: tsi switch matrix ................................ ................................ ................................ ............. 146 figure 53: example sequence in xp mode ................................ ................................ ...................... 147 figure 54: transient and static line regulation ................................ ................................ ............... 177 figure 55: transient and static load regulation ................................ ................................ .............. 177 figure 56: dialog da9053 reference board ................................ ................................ ..................... 179 figure 57: 169ld - vfbga (7 x 7 mm) package outline draw ing ................................ ..................... 180 figure 58: 169 - vfbga (11 x 11 mm) package drawing ................................ ................................ .. 181 tables table 1: regulator overview ................................ ................................ ................................ ............... 11 table 2: ballout description ................................ ................................ ................................ ................. 14 table 3: pin type definition ................................ ................................ ................................ ................ 17 table 4: absolute maximum ratings ................................ ................................ ................................ ... 18 table 5: recommended operating conditions ................................ ................................ ................... 19 table 6: current consumption ................................ ................................ ................................ ............ 19 table 7: digital i/o characteristics ................................ ................................ ................................ ...... 20 table 8: gpio characteristics ................................ ................................ ................................ ............. 21 table 9: power on reset characteristics ................................ ................................ ............................ 21 table 10: watchdog ................................ ................................ ................................ ............................ 22 table 11: hs - 2 - wire timing ................................ ................................ ................................ ................ 22 table 12: 4 - wire timing ................................ ................................ ................................ ...................... 23 table 13: oscillator characteristics ................................ ................................ ................................ ..... 24 table 14: reference voltage generation and temperature supervision ................................ ........... 24 table 15: ldo1 characteristics ................................ ................................ ................................ .......... 24 table 16: ldo2 characteristics ................................ ................................ ................................ .......... 26 table 17: ldo3 characteristics ................................ ................................ ................................ .......... 27 table 18: ldo4 characteristics ................................ ................................ ................................ .......... 28 table 19: ldo5 characteristics ................................ ................................ ................................ .......... 29 table 20: ldo6 characteristics ................................ ................................ ................................ .......... 30 table 21: ldo7 characteristics ................................ ................................ ................................ .......... 31 table 22: ldo8 characteristics ................................ ................................ ................................ .......... 32 table 23: ldo9 characteristics ................................ ................................ ................................ .......... 33 table 24: ldo10 characteristics ................................ ................................ ................................ ........ 34 table 25: ldocore characteristics ................................ ................................ ................................ .. 35 table 26: buckcore characteristics ................................ ................................ ............................... 35 table 27: buckpro characteristics ................................ ................................ ................................ .. 37 table 28: buckmem characteristics ................................ ................................ ................................ . 39 table 29: buckperi characteristics ................................ ................................ ................................ . 40 table 30: charger supply mode characteristics ................................ ................................ ................ 43 table 31: charger buck characteristics ................................ ................................ .............................. 43 table 32: voltage levels on vbat ................................ ................................ ................................ ..... 44 table 33: charging modes ................................ ................................ ................................ .................. 45 table 34: charger detection circuit ................................ ................................ ................................ .... 45 table 35: vbus charge control ................................ ................................ ................................ ......... 45 table 36: charge timer ................................ ................................ ................................ ....................... 46 table 37: dccc and active diode ................................ ................................ ................................ ...... 46 table 38: backup battery charger ................................ ................................ ................................ ...... 46 table 39: boost converter ................................ ................................ ................................ ................... 47 table 40: wled driver ................................ ................................ ................................ ........................ 48 table 41: adc ................................ ................................ ................................ ................................ ..... 48 table 42: accessory detection states ................................ ................................ ................................ 50 table 43: lpi interface signals ................................ ................................ ................................ ........... 52
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 8 of 183 ? 2016 dialog semiconductor table 44: 4 - wire clock configurations ................................ ................................ ................................ 63 table 45: wake - up events ................................ ................................ ................................ .................. 73 tabl e 46: power sequencer controlled actions ................................ ................................ .................. 75 table 47: register page 0 ................................ ................................ ................................ ................... 79 table 48: power sequencer control registers ................................ ................................ ................. 100 table 49: buck current limit and coil saturation current limit ................................ ....................... 107 table 50: power supply control registers ................................ ................................ ....................... 108 table 51: thermal charge current control ................................ ................................ ....................... 129 table 52: charging control registers ................................ ................................ ............................... 131 table 53: backup battery charging control registers ................................ ................................ ..... 136 table 54: boost and led driver control registers ................................ ................................ ........... 138 table 55: registers summary ................................ ................................ ................................ ........... 148 table 56: gp - adc control registers ................................ ................................ ................................ 149 table 57: tsi control registers ................................ ................................ ................................ ........ 154 table 58: rtc calendar and alarm control registers ................................ ................................ ..... 157 table 59: customer otp registers ................................ ................................ ................................ .. 160 table 60: recommended capacitor types: ................................ ................................ ...................... 169 table 61: recommended inductor types ................................ ................................ ......................... 170 table 62: recommended resistor types ................................ ................................ ......................... 171 table 63: recommended schottky diode and transistor types ................................ ...................... 171 table 64: example backup battery types ................................ ................................ ........................ 171 table 65: example batter y pack temperature sensor ................................ ................................ ..... 172 table 66: recommended crystal type ................................ ................................ ............................. 172 table 67: ordering information ................................ ................................ ................................ ......... 181
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 9 of 183 ? 2016 dialog semiconductor 1 terms and d efinitions adc analog to digital converter bcd binary coded decimal cc constant current cv constant voltage dccc dynamic charger current control dvc dynamic voltage control esd electrostatic discharge esr equivalent series resistance gnd ground gsm global system for mobile communication irq interrupt request ldo low dropout voltage regulator led light emitting diode ntc negative temperature coefficient otp one time programmable ov overvoltage pcb printed circuit board pfm pulse frequency modulation pmic power management integrated circuit psrr power supply rejection ratio pwm pulse width modulation rtc real time c lock tdma time division multiple access trc trimming release code usb universal serial bus
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 10 of 183 ? 2016 dialog semiconductor 2 block d iagram figure 1 : block diagram d a t a / g p i o _ 1 4 c l k / g p i o _ 1 5 n c s s i s k h s 2 - w i r e i n t e r f a c e s o v d d _ i o 1 m u l t i p l e x e d g p i o e x t e n d e r g p i o _ 1 / a d c i n 5 g p i o _ 3 / t s i y n g p i o _ 4 / t s i y p g p i o _ 2 / a d c i n 6 g p i o _ 0 / a d c i n 4 g p i o _ 6 / t s i x p g p i o _ 7 / t s i r e f g p i o _ 5 / t s i x n p i n - m u l t i p l e x w i t h g p - a d c / t s i / c o n t r o l / h s i 2 c g p i o _ 9 / p w r _ e n g p i o _ 1 1 / a c c _ i d _ d e t g p i o _ 1 3 / n v d d _ f a u l t g p i o _ 1 0 / p w r _ e n 1 g p i o _ 8 / s y s _ e n g p i o _ 1 4 / d a t a g p i o _ 1 5 / c l k g p i o _ 1 2 / g p _ f b 1 4 - w i r e / 2 - w i r e i n t e r f a c e d i g c t r l v d d c o r e v d d _ i o 2 d a 9 0 5 3 b a t t e r y s w i t c h 4 w i r e t o u c h - s c r e e n c o n t r o l l e r p o w e r m a n a g e r o n / o f f c o n t r o l r e s e t g e n e r a t i o n o t p - p r o g r a m m a b l e w a k e - u p a n d s h u t d o w n s e q u e n c i n g c o n t r o l s y s t e m m o n i t o r i n t e r r u p t h a n d l e r b a c k u p b a t t e r y c h a r g e r 1 . 1 - 3 . 1 v 2 . 2 u h d c i n _ p r o t t e m p s e n s o r v o l t a g e s u p e r - v i s i o n r t c 3 2 k h z o s c r t c d i g i t a l r e f v o l t a g e b i a s i n g c i r c u i t i n t e r n a l o s c b u c k m e m v b u c k m e m g e n e r a l p u r p o s e 1 0 b i t a d c t b a t d i g c t r l 1 . 0 u f l d o 5 1 . 2 - 3 . 6 v v b u s s e l e c t o r o v - p r o t e c t i o n n t c v l d o 5 v d d o u t v b a t 2 . 2 u h b u c k p r o v b u c k p r o 2 . 2 u h b u c k p e r i v b u c k p e r i d v s d a c 2 . 2 u h b u c k c o r e v b u c k c o r e d v s d a c l d o 3 ( d v c ) 1 . 7 2 5 - 3 . 3 v d i g c t r l 2 . 2 u f l d o 4 1 . 7 2 5 - 3 . 3 v d i g c t r l 2 . 2 u f v l d o 3 v l d o 4 v d d o u t / v b u c k x l d o 1 ( l n ) 0 . 6 - 1 . 8 v d i g c t r l 1 . 0 u f l d o 2 ( d v c ) 0 . 6 - 1 . 8 v d i g c t r l 1 . 0 u f v l d o 1 v l d o 2 l d o 6 ( l n ) 1 . 2 - 3 . 6 v d i g c t r l 2 . 2 u f l d o 8 ( l n ) 1 . 2 C 3 . 6 v d i g c t r l 2 . 2 u f l d o 9 ( l n ) 1 . 2 5 C 3 . 6 5 v d i g c t r l 2 . 2 u f l d o 1 0 ( l n ) 1 . 2 C 3 . 6 v d i g c t r l 1 . 0 u f v l d o 6 v l d o 8 v l d o 9 v l d o 1 0 v d d c o r e l d o 7 ( l n ) 1 . 2 - 3 . 6 v d i g c t r l 2 . 2 u f b o o s t c o n v e r t e r c u r r e n t c o n t r o l l e d f o r l e d b a c k l i g h t d v s d a c 4 . 7 u h 2 u f v d d o u t a c t i v e d i o d e c h a r g e r 1 0 0 m v d d c o r e v d d c o r e 3 0 u f d i s t r i b u t e d 2 . 2 u h 4 4 u f 2 2 u f 1 0 0 n f 2 . 2 u f d i g c t r l l d o c o r e 2 . 5 v 1 0 0 n f v d d o u t / v b u c k x v d d o u t / v b u c k x v l d o 7 v d d o u t / v b u c k x v d d o u t / v b u c k x v d d o u t / v b u c k x v d d r e f p o w e r p a t h p l u s d i g c t r l 3 2 k h z c r y s t a l v b b a t o u t _ 3 2 k s y s _ e n / g p i o _ 8 p w r _ e n / g p i o _ 9 p w r 1 _ e n / g p i o _ 1 0 g p _ f b 1 / g p i o _ 1 2 n r e s e t n s h u t d o w n n i r q a c c _ i d _ d e t / g p i o _ 1 1 n o n k e y / k e e p _ a c t t s i x p / g p i o _ 6 t s i x n / g p i o _ 5 t s i y p / g p i o _ 4 t s i y n / g p i o _ 3 a d c i n 4 / g p i o _ 0 a d c i n 5 / g p i o _ 1 a d c i n 6 / g p i o _ 2 n v d d _ f a u l t / g p i o _ 1 3 2 0 0 k v r e f i r e f v b u s v d d o u t / v b u c k x / v d d r e f s y s _ u p d i g c t r l v d d c o r e v m e m _ s w _ e n v m e m _ s w v p e r i _ s w _ e n v p e r i _ s w t p d + d - d i g c t r l u s b c h a r g e r c o n t r o l o v - p r o t e c t i o n d c i n s e l e c t o r d c i n v b u s _ p r o t o t p m e m o r y w a t c h d o g t i m e r v c e n t e r 4 7 0 n f 1 0 u f t s i r e f / g p i o _ 7 d i g c t r l p w r _ u p / g p _ f b 2 v d d o u t 2 2 u f 2 2 u f v d d o u t v d d o u t
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 11 of 183 ? 2016 dialog semiconductor 3 generated s upply d omains table 1 : regulator o verview regulator supplied p ins supplied v oltage (v) supplied m ax c urrent (ma) external c omponents notes buckcore vbuckcore 0.5 to 2.075 3 % accuracy 2000 2.2 h dvc, 2 mhz, 25 mv steps,dvc ramp with controlled slew rate; pull - down resistor switch off buckpro vbuckpro 0.5 to 2.075 3 % accuracy 1000 2.2 h dvc, 2 mhz, 25 mv steps, dvc ramp with controlled slew rate ; pull - down resistor switch off, common supply with buckperi buckmem vbuckmem ; vmem_sw 0.95 to 2.525 3% accuracy 1000 2.2 h dvc, 2 mhz, 25 mv steps, dvc ramp with controlled slew rate; 2 nd output with sequencer controllable switch, pull - down resistor switch off, buckperi vbuckperi ; vperi_sw 0.95 to 2.525 3 % accuracy 1000 2.2 h 2 mhz, 25 mv steps 2 nd output with sequencer controllable switch, common supply with buckpro boost ext. fet 5 to 25, regulated via current feedback 78 4.7 h current controlled boost converter for three strings of up to six serial white leds. over voltage protection via a voltage feedback pin. ldo1 vldo1 0.6 to 1.8v 3 % accuracy 40 1.0 f high pssr, low noise ldo, 50 mv steps, pull - down resistor switch off ldo2 vldo2 0.6 to 1.8 3 % accuracy 100 1.0 f dvc, digital ldo, 25 mv steps, dvc ramp with controlled slew rate, pull - down resistor switch off ldo3 vldo3 1.725 to 3.3 3 % accuracy 200 2.2 f dvc, digital ldo, 25 mv steps, dvc with controlled slew rate, common supply with ldo4 ldo4 vldo4 1.725 to 3.3 3 % accuracy 150 2.2 f digital ldo, 25 mv steps, optional hw control from gpi1, common supply with ldo3
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 12 of 183 ? 2016 dialog semiconductor regulator supplied p ins supplied v oltage (v) supplied m ax c urrent (ma) external c omponents notes ldo5 vldo5 1.2 to 3.6 3 % accuracy 100 1.0 f digital ldo, 50 mv steps, pull - down resistor switch off, optional hw control from gpi2, ldo6 vldo6 1.2 to 3.6 3 % accuracy 150 2.2 f high psrr, low noise, 50 mv steps ldo7 vldo7 1.2 to 3.6 3 % accuracy 200 2.2 f high psrr, low noise, 50 mv steps, common supply with ldo8 ldo8 vldo8 1.2 to 3.6v 3 % accuracy 200 2.2 f high psrr, low noise, 50 mv steps, common supply with ldo7 ldo9 vldo9 1.25 to 3.6v 1 % accuracy note 1 100 1.0 f high psrr, low noise, 50 mv steps, otp trimmed, optional hw control from gpi12, common supply with ldo10 ldo10 vldo10 1.2 to 3.6 3 % accuracy 250 2.2 f high psrr, low noise, 50 mv steps, common supply with ldo9 backup vbbat 1.1 to 3.1 6 470 nf 100 mv or 200 mv steps, configurable current limit between 100 and 6000 a, reverse current protection ldocore internal pmic supply 2.5 2 % accuracy 4 100 nf not for external use note 1 at default voltage (1 % accuracy requires vldo9 > 1.5 v) .
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 13 of 183 ? 2016 dialog semiconductor 4 pad d escription figure 2 : da9053 b allout ( v iew f rom to p, b alls t hrough p ackage) 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 a n c v r e f d c i n _ p r o t d c i n _ p r o t v b u s _ p r o t v b u s _ p r o t v c e n t r e v s w v s w v d d o u t v d d o u t v b a t v b a t b x o u t v b b a t d c i n _ s e l d c i n v b u s _ s e l v b u s n c n c n c g p _ f b 1 _ g p i o _ 1 2 a d _ c o n t v m e m _ s w d m i n u s c x i n v d d _ r e f n c a d c i n 6 _ g p i o _ 2 a d c i n 5 _ g p i o _ 1 a d c i n 4 _ g p i o _ 0 n c n c n c p w r _ e n _ g p i o _ 9 n v d d _ f a u l t _ g p i o _ 1 3 v b u c k m e m d p l u s d v l d o 1 v d d c o r e n c n c i r e f v s s _ n o i s y v s s _ n o i s y n c n c s y s _ e n _ g p i o _ 8 n s h u t d o w n v p e r i _ s w v d d b u c k _ c o r e e v d d _ l d o 2 v d d _ l d o 1 n c n c v s s _ n o i s y v s s _ n o i s y v s s _ n o i s y v s s _ n o i s y v s s _ n o i s y n i r q n c v b u c k p e r i v d d b u c k _ c o r e f v l d o 5 v l d o 2 n c n c v s s _ n o i s y v s s _ n o i s y v s s _ n o i s y v s s _ n o i s y v s s _ n o i s y n r e s e t n c v b u c k c o r e s w b u c k c o r e g v l d o 6 v d d _ l d o 5 n c n c v s s _ q u i e t v s s _ q u i e t v s s _ n o i s y v s s _ n o i s y v s s _ n o i s y n c n c n c s w b u c k c o r e h v l d o 4 v d d _ l d o 6 n c n c v s s _ q u i e t v s s _ q u i e t v s s _ n o i s y v s s _ n o i s y v s s _ n o i s y n c n c n c s w b u c k p r o j v l d o 3 v d d _ l d o 3 _ 4 n c n c v s s _ q u i e t v s s _ q u i e t v s s _ n o i s y v s s _ n o i s y v s s _ n o i s y p w r _ u p _ g p _ f b 2 n c n c v d d b u c k _ p e r _ p r o k v l d o 7 v d d _ l d o 7 _ 8 n c v d d _ i o 2 t s i x n _ g p i o _ 5 t s i y n _ g p i o _ 3 t s i x p _ g p i o _ 6 t s i y p _ g p i o _ 4 t s i r e f _ g p i o _ 7 s i n c s o u t 3 2 k v d d b u c k _ p e r _ p r o l v l d o 8 p w r 1 _ e n _ g p i o _ 1 0 a c c _ i d _ d e t _ g p i o _ 1 1 v d d _ i o 1 t p t b a t l e d 3 _ i n l e d 2 _ i n n c s o s k s y s _ u p s w b u c k p e r i m v l d o 9 c l k _ g p i o _ 1 5 v d d _ l d o 9 _ 1 0 n c n c n c n c n c l e d 1 _ i n s w _ b o o s t n o n k e y _ k e e p _ a c t v b u c k p r o s w b u c k m e m n d a t a _ g p i o _ 1 4 v l d o 1 0 n c n c n c n c n c n c b o o s t _ s e n s e _ n b o o s t _ s e n s e _ p b o o s t _ p r o t n c v d d b u c k _ m e m
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 14 of 183 ? 2016 dialog semiconductor table 2 : ballo ut d escription pad pad n ame type description power manager m11 nonkey di o n /off key with optional long press shutdown/ hardware input for watchdog supervision d10 sys_en di/dio hardware enable of power domain system/gpio_8 c10 pwr_en di/dio hardware enable of power domain power/gpio_9 l2 pwr1_en di/dio hardware enable of power domain power1/gpio_10 with high - power output and blinking feature, input for power sequencer wait id l3 acc_id_det di/dio acc_id_det accessory detection circuitry/gpio_11 with high - power output and blinking feature d11 nshutdown di active low input from switch or error indication line from host to initiate shutdown f10 nreset do active low reset towards host b10 gp_fb1 do/dio status indication towards host for a valid wakeup event (ext_wakeup) or indicator for ongoing power mode transition (ready) /gpio_12, enables hw control of ldo9 e10 nirq do active low irq line towards host c11 nvdd_fault do/dio active low indication for low supply voltage/gpio_13 l12 sys_up do sequencer status indicator: all system ids powered up j10 pwr_up do/do sequencer status indicator: all power ids powered up (pwr_up) or programmable level controlled from the power sequencer (gp_fb2) l4 vdd_io1 ps first supply i/o voltage rail k4 vdd_io2 ps alternate supply i/o voltage rail l5 tp dio test pin, enables power commander boot mode 4 - w ire/2 - w ire i nterfaces l10 so dio 4 - wire d ata output, 2 - wire d ata k10 si di 4 - wire d ata input l11 sk di 4 - wire , 2 - wire c lock k11 ncs di 4 - wire c hip select n1 data dio hs - 2 - wire d ata [ gpio_14 ] (enables reset if long press in parallel with gpi15) with high - power output and pwm led control m2 clk di hs - 2 - wire c lock [ gpio_15 ] (enables reset if long press in parallel with gpi14) ) with high - power output and pwm led control
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 15 of 183 ? 2016 dialog semiconductor pad pad n ame type description voltage r egulators d1 vldo1 ao output v oltage from ldo1 e2 vdd_ldo1 ps supply voltage for ldo1 f2 vldo2 ao output voltage from ldo2 e1 vdd_ldo2 ps supply voltage for ldo2 j1 vldo3 ao output voltage from ldo3 h1 vldo4 ao output voltage from ldo4 j2 vdd_ldo3_4 ps supply voltage for ldo3 and ldo4 f1 vldo5 ao output voltage from ldo5 g2 vdd_ldo5 ps supply voltage for ldo5 g1 vldo6 ao output voltage from ldo6 h2 vdd_ldo6 ps supply voltage for ldo6 k1 vldo7 ao output voltage from ldo7 l1 vldo8 ao output voltage from ldo8 k2 vdd_ldo7_8 ps supply voltage for ldo7 and ldo8 m1 vldo9 ao output voltage from ldo9 n2 vldo10 ao output voltage from ldo10 m3 vdd_ldo9_10 ps supply voltage for ldo9 and ldo10 d2 vddcore ao supply for internal circuitry c2 vdd_ref ao switched supply from vbat, vbus or vbackup d c /d c b uck c onverters f12 vbuckcore ai sense node for dvc dc/dc buckcore f - g13 swbuckcore ao switching node for buckcore m12 vbuckpro ai sense node for dvc dc/dc buckpro h13 swbuckpro ao switching node for buckpro c12 vbuckmem ai sense node for dvc dc/dc buckmem and input for power switch (sequencer controlled) b12 vmem_sw ps power switch output from buckmem m13 swbuckmem ao switching node for buckmem e12 vbuckperi ai sense node for dc/dc buckperi and input for power switch (sequencer controlled) d12 vperi_sw ps power switch output from buckperi l13 swbuckperi ao switching node for buckperi d - e13 vddbuck_core ps supply voltage for buckcore j - k13 vddbuck_per_pro ps supply voltage for buckperi and buckpro to be connected to vddout n13 vddbuck_mem ps supply voltage for buckmem to be connected to vddout
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 16 of 183 ? 2016 dialog semiconductor pad pad n ame type description reference v oltage g eneration a2 vref aio reference voltage output , d ecouple with 100 nf d5 iref ao connection for bias setting , c onfigure with high precision 200 k? resistor internal o scillator c1 xin aio 32 khz c rystal connection adjust with 10 pf b1 xout aio 32 khz c rystal connection adjust with 10 pf k12 out_32k do 32 khz o scillator buffer output charger b5 vbus_sel ao control for external over voltage protection and input selection of vbus to be connected to gate of pfet a5 - 6 vbus_prot ps overvoltage protected vbus charger input b6 vbus ps usb or wall charger input b3 dcin_sel ao control for external over voltage protection and input selection of dcin to be connected to gate of pfet a3 - 4 dcin_prot ps overvoltage protected dcin charger input b4 dcin ps wall charger input a7 vcenter ps protected input for swit ching charger (decouple with 10 f) a8 - 9 vsw ps switching node for charger buck a10 - 11 vddout ps system power supply output b11 ad_cont ao active diode controller output to be connected to gate of pfet (leave unconnected, if not used) a12 - 13 vbat ps connection to main battery boost c onverter and led c urrent s inks m10 sw_boost ao boost switching output to be connected to gate of nfet n10 boost_sense_p ai high side sense connected to boost isat current protection resistor, stabilize with capacitor n9 boost_sense_n ai low side sense connected to boost isat current protection resistor n11 boost_prot ai over voltage protection input requires external resistor voltage divider m9 led1_in ai connection to led string 1 provides current controlled sink via logarithmic idac l8 led2_in ai connection to led string 2 provides current controlled sink via logarithmic idac l7 led3_in ai connection to led string 3 provides current controlled sink via logarithmic idac with pwm only led control usb c harger c ontrol c13 d+ aio usb d+ b13 d - aio usb d -
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 17 of 183 ? 2016 dialog semiconductor pad pad n ame type description general p urpose adc and t ouch s creen i nterface l6 tbat aio connection to battery ntc resistor c6 adcin4 ai/dio connection to gp adc auto channel 4 with threshold irq and resistor measurement option/gpio_0 c5 adcin5 ai/dio connection to gp adc channel 5 with 1.2 v hw comparator irq/gpio_1, enables hw control of ldo4 c4 adcin6 ai/dio connection to gp adc channel 6/gpio_2 enables hw control of ldo5 k6 tsiyn aio/dio tsi interface connection to yn terminal of touch screen k8 tsiyp aio/dio tsi interface connection to yp terminal of touch screen k5 tsixn aio/dio tsi interface connection to xn terminal of touch screen k7 tsixp aio/dio tsi interface connection to xp terminal of touch screen k9 tsref ps tsi interface reference voltage backup b attery c harger b2 vbbat aio backup battery connection c oin - c ell or s uper - c ap vss d6 - d7, e5 - f9, g7 - j9 vss_noisy vss vss connection for noisy circuits (bucks) to be connected to main ground plane of pcb for optimum electrical and thermal performance g5 - j6 vss_quiet vss vss connection for quiet circuits (ldos) to be connected to main ground plane of pcb for optimum electrical and thermal performance a1, b7 - c9, d8 - d9, c3 - k3, d4 - j4, g10 - h10, e11 - j11, g12 - j12, l9, m4 - m8, n3 - n8, n12 nc non - connected balls floating in package, can be freely connected on pcb, recommended to be connected to ground plane for optimum noise and thermal performance table 3 : pin t ype d efinition pin t ype description pin t ype description di digital input ai analog input do digital output ao analog output dio digital input/output aio analog input/output diod digital input/output open drain bp backdrive protection ps power supply vss power supply
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 18 of 183 ? 2016 dialog semiconductor 5 electrical c haracteristics 5.1 absolute m aximum r atings the maximum continuous charger voltage must be less than 5.5 v , the over - voltage protection ( ovp ) circuit will help protect against transients above this level minimi z ing effects on operation lifetime. vddout must not be driven from an external supply if the charger buck is used . table 4 : absolute m aximum r atings parameter symbol conditions note 1 min max unit storage temperature - 40 +95 c j unction temperature t j - 40 + 140 note 2 c s upply voltage v bat , v bus_prot , d cin_prot , v ddout , v dd_ref - 0.3 5.5 v supply voltage charger v bus , d cin - 0.3 12 v supply voltage ldo and b uck input pins (except listed below) - 0.3 v ddout + 0.3 v, 5 v max v supply voltage all pins ( except listed above) - 0.3 v ddout + 0.3 v, 5 v max v esd susceptibility human body model 2 kv note 1 stresses beyond those listed under absolute m aximum r atings may cause permanent damage to the device. these are stress ratings only, so functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specification are not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note 2 see section 5.11 for more details.
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 19 of 183 ? 2016 dialog semiconductor 5.2 recommended o perating c onditions all v oltages are referenced to v ss unless otherwise stated. currents flowing into da9053 are deemed p ositive, currents flowing out are dee med negative. all parameters are valid over the recommended temperature range and power supply range unless otherwise noted. note t he power dissipation must be limited to avoid overheating of da9053. the maximum power dissipation should not be reached wi th maximum ambient temperature. table 5 : recommended o perating c onditions parameter symbol conditions min max unit supply voltage v bat 0 4.4 v supply voltage charger v bus , d cin 0 5.5 v supply voltage io v dd_io1 , v dd_io2 1.2 3.6 note 1 v operating junction temperature t j - 40 +125 c maximum power dissipation 7x7 package. derating factor above ta = 70 c: 21 mw/ c 1.14 w package thermal resistance note 2 7x7 package. 48 c /w maximum power dissipation 11 x 11 package derating factor above ta = 70 c: 40 mw/ c 2.2 w package thermal resistance note 2 11x11 package 25 c /w note 1 v dd_io must not exceed v ddout . note 2 jedec 4 layer board, still air, influence d by pcb technology and layout. the numbers of supplies, that can be used at the same time at maximum dissipation power is limited by the thermal resistance of the package and the pcb layout . 5.3 current c onsumption table 6 : current c onsumption operating m ode conditions (ta = 25 c ) min typ max u nit no - power m ode detection circuits running, oscillator off 15 a reset m ode v dd_ref > 2.2 v, bucks and ldos off ( except ldocore), rtc unit on 45 ( note 1 ) a power - down mode (standby) v dd_ref > 2.8 v, supplies off ( except ldocore), all blocks in powerdown mode, rtc unit on 45 a power - down mode (hibernate) buckcore, ldocore, ldo2, 4, 5 enabled, rtc and gpio unit on 190 ( note 2 ) a active m ode all supplies, gpio, rtc and gp - adc on 460 a
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 20 of 183 ? 2016 dialog semiconductor note 1 v dd_ref > 2.5 v if not supplied from backup battery . note 2 enabled bucks are set to forced sleep mode, setting 00 . 5.4 digital i/o c haracteristics unless otherwise noted, the following is valid for t j = - 40 c to +125 oc , v dd_ref = 2.8 v to 5.5 v. table 7 : d igital i/o c haracteristics parameter symbol conditions min typ max unit gpi0 C gpi15, nonkey, nshutdown sys_en, pwr_en, pwr1_en, clk, data i nput h igh v oltage v ih vddcore mode vdd_io2 mode 1.0 0.7*vdd_io2 v ddout v gpi0 C gpi15, nonkey, nshutdown sys_en, pwr_en, pwr1_en clk, data i nput l ow v oltage v il vddcore mode vdd_io2 mode 0.4 0.3*v dd_io2 v sk, ncs, si i nput h igh v oltage v ih vdd_io1 mode vdd_io2 mode 0.7*v dd_io1 0.7*v dd_io2 v ddout v sk, ncs, si i nput l ow v oltage v il vdd_io1 mode vdd_io2 mode 0.3*v dd_io1 0.3*v dd_io2 v gpo0 C gpo15, nvdd_fault, so nreset, nirq sys_up, pwr_up, gp_fb2, out_32k o utput h igh v oltage v oh @ 1 ma vdd_io1 mode vdd_io2 mode 0.8*v dd_io1 0.8*v dd_io2 v ddout v gpo0 C gpo15, data, so nreset, nirq o utput h igh v oltage v oh 0 open drain v ddout v gpo0 C gpo15, data, so, nvdd_fault, nreset ( note 1 ), nirq, sys_up, pwr_up, gp_fb2, out_32k o utput l ow v oltage v ol @ 1 ma 0.3 v
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 21 of 183 ? 2016 dialog semiconductor note 1 for v supply < 1.5 v th e source current for min 0.8 * vdd is limited to 0.5 ma . it is good practice to allow a 10 % voltage margin when running at maximum temperatures to allow for worse case process variation . 5.5 gpio c haracteristics unless otherwise n oted, the following is valid for t j = - 40 c to +125 oc , v dd_ref = 2.8 v to 5.5 v. table 8 : gpio c haracteristics parameter symbol conditions min typ max unit sink current capability gpo 14, 15 vgpio = 0.1 v 30 note 1 ma sink current capability gpo 10,11 vgpio = 0.5 v 15 ma source current capability gpo 10,11,14,15 vgpio = v dd_io1/2 - 0.5 v - 4 note 2 ma sink current capability gpo 09, 1213 vgpio = 0.3 v 1 ma source current capability gpo 09, 1213 vgpio = v dd_io1/2 - 0.5 v - 1 note 2 ma gpo pull - up resistor note 3 = 1.5 v v dd_io1/2 = 1.8 v = 3.3 v 100 70 25 180 120 40 300 170 60 k ? d+/d - input impedance 10 2 m ? ? pf note 1 at low v dd_ref values and high temperatures, the sink current capability will be reduced . note 2 for v dd_io1/2 < 1.5 v the source current for min 0.8 * v dd is limited to 0.8 ma . note 3 v(pad) = 0 v . 5.6 power on r eset table 9 : power on r eset c haracteristics parameter symbol min typ max unit deep d ischarge l ockout l ower t hreshold v por_lower 2.0 v deep d ischarge l ockout u pper t hreshold v por_upper 2.5 v under v oltage l ower t hreshold v dd_fault_lower 2.8 2. 8 3.15 v under voltage l ower t hreshold a ccuracy v dd_fault_lower a ccuracy +/ - 2 % under v oltage u pper t hreshold v dd_fault_upper v dd_fault_lower + 0.15 v charger b uck under v oltage v ddout_min 3.35 3.40 3.45 v
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 22 of 183 ? 2016 dialog semiconductor 5.7 watchdog table 10 : watchdog parameter symbol conditions min typ max unit minimum w atchdog time t wdmin 0.18 0.256 0.33 s maximum w atchdog time t wdmax 1.44 2.048 2.64 s 5.8 po wer m anager and hs - 2 - w ire c ontrol b us figure 3 : 2 - w ire c ontrol bus t iming d iagram table 11 : hs - 2 - w ire t iming parameter symbol min typ max unit bus free time stop to start 1.3 s bus line capacitive load 100 pf standard / fast m ode clk clock frequency 1 400 khz bus free time stop to start 1.3 s start condition set - up time 0.6 s start condition hold time sth 0.6 s clk low time clkl 1.3 s clk high time clkh 0.6 s 2 - wire clk and data rise/fall time 300 ns data set - up time dst 100 ns data hold - time dht 0 ns stop condition set - up time tss 0.6 s c l k / s k d a t a / s o s t h c l k l c l k h d s t t s s d h t
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 23 of 183 ? 2016 dialog semiconductor parameter symbol min typ max unit high speed m ode clk clock frequency 1 1700 khz start condition set - up time 160 ns start condition hold time sth 160 ns clk low time clkl 160 ns clk high time clkh 60 ns hs - 2 - wire clk rise/fall time 40 ns hs - 2 - wire data rise/fall time 80 ns data set - up time dst 10 ns data hold - time dht 10 ns stop condition set - up time tss 16 ns 5.9 4 - w ire c ontrol b us t iming figure 4 : 4 - w ire c ontrol b us t iming d iagram note the above timing is valid for active low and high cs . table 12 : 4 - w ire t iming parameter symbol label in figure 4 min typ max unit cycle t ime t c 1 70 ns enable lead time t css 2, from cs active to first sk edge 20 ns enable lag time t scs 3, from last sk edge to cs idle 20 ns clock low time t cl 4 0.4 * t c ns clock high time t ch 5 0.4 * t c ns 1 2 4 5 1 0 8 9 1 1 3 a 6 a 5 a 4 b i t 7 r / w b i t 1 l s b l s b b i t 1 a d d r e s s r / w d a t a s o s i s k n c s 7 6
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 24 of 183 ? 2016 dialog semiconductor parameter symbol label in figure 4 min typ max unit data i n setup time t sis 6 5 ns data i n hold time t sih 7 5 ns data o ut valid time t sov 8 22 ns data o ut hold time t soh 9 6 ns data access time t h 10 22 ns cs inactive time t wcs 11 20 ns 5.10 oscillator table 13 : oscillator c haracteristics parameter symbol conditions min typ max unit internal oscillator frequency b efore trimming a fter trimming 1.4 1.9 2.0 2.0 2.6 2.1 mhz 5.11 reference v oltage g eneration and t emperature s upervision table 14 : reference v oltage g eneration and t emperature s upervision parameter symbol conditions min typ max unit reference v oltage vref p in - 1.25 % 1.2 +1 % v vref decoupling capacitor 100 nf reference c urrent resistor iref p in - 1 % 200 +1 % k ? thermal s hutdown t over 125 140 155 oc charge current reduction t chargelow 75 90 115 oc charge suspend t chargesuspend 105 120 135 oc hysteresis 10 oc 5.12 ldo v oltage r egulators 5.12.1 ldo1 table 15 : ldo1 c haracteristics parameter symbol conditions min typ max unit input voltage v dd (if supplied from buck) 2.0 (1.5) v ddout + 0.3 v, 5 v m ax v output voltage v ldo1 i out = i max 0.6 note 1 1.8 v output accuracy i out = i max - 3 note 2 +3 % stabilization c out (including voltage and temperature coefficient @ - 55 % 1.0 +35 % f
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 25 of 183 ? 2016 dialog semiconductor parameter symbol conditions min typ max unit capacitor configured vldo1) esr of capacitor f > 1 mhz 0.1 ? maximum output current i max v dd 1.8 v 40 note 3 ma short circuit current i short 80 ma dropout voltage v dropout v dd > 2.15 v i out = i max (v dd = 2.0 v i out = 0.4 * i max or v dd = 1.5 v i out = 0.25 * i max ) 200 100 350 150 mv static line regulation vs line v dd = 3.0 v to 5.0 v i out = i max 5 20 mv static load regulation vs load i out = 1 ma to i max 5 20 mv line transient response vtr line v dd = 3.0 v to 3.6 v i out = i max t r = t f = 10 s 5 20 mv load transient response vtr load v dd = 3.6 v i out = 1 ma to i max t r = t f = 1 s 15 50 mv psrr psrr f = 10 hz to 10 khz v dd = 3.6 v 50 60 db output noise n f = 10 hz to 100 khz v dd = 3.6 v i out = 5 ma to i max 80 vrms quiescent current in on m ode iq on note 4 8 a + 1.25 % of i out a quiescent current in off mode iq off 1 a turn on time t on 10 % to 90 % 300 s turn off time t off 90 % to 10 % 10 ms pull down resistance in off mode r off can be switched off via ldo1_pd_dis 100 ? note 1 programmable in 50 mv voltage steps, maximum output voltage is determined by v dd - dropout voltage. note 2 sourced from ldocore band gap . note 3 max. current is 10 ma if supplied from v dd_ref . note 4 internal regulator current flowing to ground .
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 26 of 183 ? 2016 dialog semiconductor 5.12.2 ldo2 table 16 : ldo 2 c haracteristics parameter symbol conditions min typ max unit input voltage v dd (if supplied from buck) 2.8 (1.5) v ddout + 0.3 v, 5 v max v output voltage v ldo2 i out = i max 0.6 note 1 1.8 v output accuracy i out = i max - 3 +3 % stabilization capacitor c out (including voltage and temperature coefficient @ configured v ldo2 ) - 55% 1.0 +35 % ? f esr of capacitor f > 1 mhz 0.1 ? maximum output current i max v dd 1.8 v 100 ma short circuit current i short 200 ma dropout voltage v dropout i out = i max (for v dd = 1.5 v i out = i max /3) 100 200 mv static line regulation vs line v dd = 3.0 v to 5.0 v i out = i max 5 20 mv static load regulation vs load i out = 1 ma to i max 5 20 mv line transient response vtr line v dd = 3.0 v to 3.6 v i out = i max t r = t f = 10 s 5 20 mv load transient response vtr load v dd = 3.6 v i out =1 ma to i max t r = t f = 1 s 15 50 mv psrr psrr f = 10 hz to 10 khz v dd = 3.6 v 40 60 db quiescent current in on mode iq on note 2 8 a +0.6 % of i out a quiescent current in off mode iq off 1 a turn on time t on 10 % to 90 % 500 s turn off time t off 90 % to 10 % 10 ms pull down resistance in off mode r off can be switched off via ldo2_pd_dis 100 ? note 1 programmable in 25 mv voltage steps, maximum output voltage is determined by v dd - dropout voltage . note 2 internal regulator current flowing to ground .
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 27 of 183 ? 2016 dialog semiconductor 5.12.3 ldo3 table 17 : ldo 3 c haracteristics parameter symbol conditions min typ max unit input voltage v dd (if supplied from buck) 2.8 (1.9) v ddout + 0.3 v, 5 v m ax v output voltage v ldo3 i out = i max 1.725 note 1 3.3 v output accuracy i out = i max - 3 +3 % stabilization capacitor c out (including voltage and temperature coefficient @ configured v ldo3 ) - 55 % 2.2 +35 % ? f esr of capacitor f > 1 mhz 0.1 ? maximum output current i max 200 ma short circuit current i short 400 ma dropout voltage v dropout i out = i max (for v dd = 1.9 v i out = i max *2/3) 100 150 mv static line regulation vs line v dd = 3.0 v to 5.0 v i out = i max 5 20 mv static load regulation vs load i out = 1 ma to i max 5 20 mv line transient response vtr line v dd = 3.0 v to 3.6 v i out = i max t r = t f = 10 s 5 20 mv load transient response vtr load v dd = 3.6 v i out = 1 ma to i max t r = t f = 1 s 20 50 mv psrr psrr f = 10 hz to 10 khz v dd = 3.6 v 40 60 db quiescent current in on mode iq on note 2 8 a +0.3 % of i out a quiescent current in off mode iq off 1 a turn on time t on 10 % to 90 % 300 s turn off time t off 90 % to 10 % 10 ms pull down resistance in off mode r off 100 ? note 1 programmable in 25 mv voltage steps, maximum output voltage is determined by v dd - dropout voltage . note 2 internal regulator current flowing to ground .
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 28 of 183 ? 2016 dialog semiconductor 5.12.4 ldo4 table 18 : ldo 4 c haracteristics parameter symbol conditions min typ max unit input voltage v dd (if supplied from buck) 2.8 (1.9) v ddout + 0.3 v, 5 v m ax v output voltage v ldo4 i out = i max 1.725 note 1 3.3 v output accuracy i out = i max - 3 +3 % stabilization capacitor c out (including voltage and temperature coefficient @ configured vldo4) - 55 % 2.2 +35 % ? f esr of capacitor f > 1 mhz 0.1 ? maximum output current i max 150 ma short circuit current i short 300 ma dropout voltage v dropout i out = i max (for v dd = 1.9 v i out = i max * 2/3) 100 150 mv static line regulation vs line v dd = 3.0 v to 5.0 v i out = i max 5 20 mv static load regulation vs load i out = 1 ma to i max 5 20 mv line transient response vtr line v dd = 3.0 v to 3.6 v i out = i max t r = t f = 10 s 5 20 mv load transient response vtr load v dd = 3.6 v i out = 1 ma to i max t r = t f = 1 s 15 50 mv psrr psrr f = 10 hz to 10 khz v dd = 3.6 v 40 60 db quiescent current in on mode iq on note 2 8 a +0.5 % of i out a quiescent current in off mode iq off 1 a turn on time t on 10 % to 90 % 300 s turn off time t off 90 % to 10 % 10 ms pull down resistance in off mode r off 100 ? note 1 programmable in 25 mv voltage steps, maximum output voltage is determined by v dd - dropout voltage . note 2 internal regulator current flowing to ground .
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 29 of 183 ? 2016 dialog semiconductor 5.12.5 ldo5 table 19 : ldo 5 c haracteristics parameter symbol conditions min typ max units input voltage v dd (if supplied from buck) 2.8 (1.5) v ddout + 0.3 v, 5 v m ax v output voltage v ldo5 i out = i max 1.2 note 1 3.6 v output accuracy i out = i max - 3 +3 % stabilization capacitor c out (including voltage and temperature coefficient @ configured v ldo5 ) - 55 % 1.0 +35 % ? f esr of capacitor f > 1 mhz 0.1 ? maximum output current i max v dd 1.8 v 100 ma short circuit current i short 200 ma dropout voltage v dropout i out = i max (for v dd = 1.5 v i out = i max /3) 100 200 mv static line regulation vs line v dd = 3.0 v to 5.0 v i out = i max 5 20 mv static load regulation vs load i out = 1 ma to i max 5 20 mv line transient response vtr line v dd = 3.0 v to 3.6 v i out = i max t r = t f = 10 s 5 20 mv load transient response vtr load v dd = 3.6 v i out = 1 ma to i max t r = t f = 1 s 15 50 mv psrr psrr f =10 hz to 10 khz v dd =3.6 v, i out = i max /2 40 60 db quiescent current in on mode iq on note 2 8 a +0.7 % of i out a quiescent current in off mode iq off 1 a turn on time t on 10 % to 90 % 200 s turn off time t off 90 % to 10 % 10 ms pull down resistance in off mode r off can be switched off via ldo5_pd_dis 100 ? note 1 programmable in 50 mv voltage steps, maximum output voltage is determined by v dd - dropout voltage . note 2 internal regulator current flowing to ground .
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 30 of 183 ? 2016 dialog semiconductor 5.12.6 ldo6 table 20 : ldo 6 c haracteristics parameter symbol conditions min typ max units input voltage v dd (if supplied from buck) 2.8 (1.5) v ddout + 0.3 v, 5 v m ax v output voltage v ldo6 i out = i max 1.2 note 1 3.6 v output accuracy i out = i max - 3 +3 % stabilization capacitor c out (including voltage and temperature coefficient @ configured v ldo6 ) - 55 % 2.2 +35 % ? f esr of capacitor f > 1 mhz 0.1 ? maximum output current i max v dd 1.8 v 150 ma short circuit current i short 300 ma dropout voltage v dropout i out = i max (for vdd = 1.5 v i out = i max /3 100 150 mv static line regulation vs line v dd = 3.0 v to 5.0 v i out = i max 5 20 mv static load regulation vs load i out = 1 ma to i max 5 20 mv line transient response vtr line v dd = 3.0 v to 3.6 v i out = i max t r = t f = 10 s 5 20 mv load transient response vtr load v dd = 3.6 v i out =1 ma to i max t r = t f = 1 s 15 50 mv psrr psrr f = 10 hz to 10 khz v dd = 3.6 v, i out = i max /2 60 70 db output noise n f = 10 hz to 100 khz v dd = 3.6 v i out = 5 ma to i max 80 vrms quiescent current in on mode iq on note 2 8 a +0.5 % of i out a quiescent current in off mode iq off 1 a turn on time t on 10 % to 90 % 200 s turn off time t off 90 % to 10 % 10 ms pull down resistance in off mode r off 100 ?
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 31 of 183 ? 2016 dialog semiconductor note 1 programmable in 50 mv voltage steps, maximum output voltage is determined by v dd - dropout voltage. note 2 internal regulator current flowing to ground . 5.12.7 ldo7 table 21 : ldo 7 c haracteristics parameter symbol conditions min typ max unit input voltage v dd (if supplied from buck) 2.8 (1.5) v ddout + 0.3 v, 5 v m ax v output voltage v ldo7 i out = i max 1.2 note 1 3.6 v output accuracy i out = i max - 3 +3 % stabilization capacitor c out (including voltage and temperature coefficient @ configured v ldo7 ) - 55 % 2.2 +35 % ? f esr of capacitor f > 1 mhz 0.1 ? maximum output current i max v dd 1.8 v 200 ma short circuit current i short 400 ma dropout voltage v dropout i out = i max (for v dd = 1.5 v i out = i max /3) 100 150 mv static line regulation vs line v dd = 3.0 v to 5.0 v i out = i max 5 20 mv static load regulation vs load i out = 1 ma to i max 5 20 mv line transient response vtr line v dd = 3.0 v to 3.6 v i out = i max t r = t f = 10 s 5 20 mv load transient response vtr load v dd = 3.6 v i out = 1 ma to i max t r = t f = 1 s 20 50 mv psrr psrr f = 10 hz to 10 khz v dd = 3.6 v, i out = i max /2 60 70 db output noise iq on f = 10 hz to 100 khz v dd = 3.6 v i out = 5 ma to i max 80 vrms quiescent current in on mode iq off note 2 8 a +0.4 % of i out a quiescent current in off mode t on 1 a turn on time t off 10 % to 90 % 600 s turn off time r off 90 % to 10 % 10 ms
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 32 of 183 ? 2016 dialog semiconductor parameter symbol conditions min typ max unit pull down resistance in off mode 100 ? note 1 programmable in 50 mv voltage steps, maximum output voltage is determined by v dd - dropout voltage . note 2 internal regulator current flowing to ground . 5.12.8 ldo8 table 22 : ldo 8 c haracteristics parameter symbol conditions min typ max unit input voltage v dd (if supplied from buck) 2.8 (1.5) v ddout + 0.3 v, 5 v m ax v output voltage v ldo8 i out = i max 1.2 note 1 3.6 v output accuracy i out = i max - 3 +3 % stabilization capacitor c out (including voltage and temperature coefficient @ configured v ldo8 ) - 55 % 2.2 +35 % ? f esr of capacitor f > 1 mhz 0.1 ? maximum output current i max vdd 1.8 v 200 ma short circuit current i short 400 ma dropout voltage v dropout i out = i max (for v dd = 1.5 v i out = i max /3) 100 150 mv static line regulation vs line v dd = 3.0 v to 5.0 v i out = i max 5 20 mv static load regulation vs load i out = 1 ma to i max 5 20 mv line transient response vtr line v dd = 3.0 v to 3.6 v i out = i max t r = t f = 10 s 5 20 mv load transient response vtr load v dd = 3.6 v i out = 1 ma to i max t r = t f = 1 s 20 50 mv psrr psrr f = 10 hz to 10 khz v dd = 3.6 v, i out = i max /2 60 70 db output noise n f = 10 hz to 100 khz v dd = 3.6 v i out = 5 ma to i max 80 vrms quiescent current in on mode iq on note 2 8 a +0.4 % of i out a quiescent current in iq off 1 a
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 33 of 183 ? 2016 dialog semiconductor parameter symbol conditions min typ max unit off mode turn on time t on 10 % to 90 % 200 s turn off time t off 90 % to 10 % 10 ms pull down resistance in off mode r off 100 ? note 1 programmable in 50 mv voltage steps, maximum output voltage is determined by v dd - dropout voltage . note 2 internal regulator current flowing to ground . 5.12.9 ldo9 table 23 : ldo 9 c haracteristics parameter symbol conditions min typ max unit input voltage v dd (if supplied from buck) 2.8 (1.5) v ddout + 0.3 v,5 v m ax v output voltage v ldo9 i out = i max 1.25 note 1 3.6 v output accuracy i out = i max - 1 +1 % stabilization capacitor c out (including voltage and temperature coefficient @ configured vldo9) - 55 % 1.0 +35 % ? f esr of capacitor f > 1 mhz 0.1 ? maximum output current i max v dd 1.8 v 100 ma short circuit current i short 200 ma dropout voltage v dropout i out = i max (for vdd = 1.5 v i out = i max /3) 100 200 mv static line regulation vs line v dd = 3.0 v to 5.0 v i ou t = i max 5 20 mv static load regulation vs load i out = 1 ma to i max 5 20 mv line transient response vtr line v dd = 3.0 v to 3.6 v i out = i max t r = t f = 10 s 5 20 mv load transient response vtr load v dd = 3.6 v i out = 1 ma to i max t r = t f = 1 s 15 50 mv psrr psrr f = 10 hz to 10 khz v dd = 3.6 v, i out = i max /2 60 70 db output noise n f = 10 hz to 100 khz v dd = 3.6 v i out = 5 ma to i max 80 vrms quiescent current in on mode iq on note 1 8 a +0.7 % a
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 34 of 183 ? 2016 dialog semiconductor parameter symbol conditions min typ max unit of i out quiescent current in off mode iq off 1 a turn on time t on 10 % to 90 % 200 s turn off time t off 90 % to 10 % 10 ms pull down resistance in off mode r off 100 ? note 1 programmable in 50 mv voltage steps, max output voltage is determined by v dd - dropout voltage. note 2 i nternal regulator current flowing to ground . 5.12.10 ldo10 table 24 : ldo 10 c haracteristics parameter symbol conditions min typ max unit input voltage v dd (if supplied from buck) 2.8 (1.5) v ddout + 0.3 v, 5 v m ax v output voltage v ldo10 i out = i max 1.2 note 1 3.6 v output accuracy i out = i max - 3 +3 % stabilization capacitor c out (including voltage and temperature coefficient @ configured v ldo10 ) - 55 % 2.2 +35 % ? f esr of capacitor f > 1 mhz 0.1 ? maximum output current i max v dd 1.8 v 250 ma short circuit current i short 500 ma dropout voltage v dropout i out = i max (for v dd < 1.8 v i out = i max /3) 100 150 mv static line regulation vs line v dd = 3.0 v to 5.0 v i out = i max 5 20 mv static load regulation vs load i out = 1 ma to i max 5 20 mv line transient response vtr line v dd = 3.0 v to 3.6 v i out = i max t r = t f = 10 s 5 20 mv load transient response vtr load v dd = 3.6 v i out = 1 ma to i max t r = t f = 1 s 30 50 mv psrr psrr f = 10 hz to 10 khz v dd = 3.6 v, i out = i max /2 60 70 db output noise n f = 10 hz to 100 khz 80 vrms
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 3 5 of 183 ? 2016 dialog semiconductor parameter symbol conditions min typ max unit v dd = 3.6 v i out = 5 ma to i max quiescent current in on mode iq on note 2 8 a +0.3 % of i out a quiescent current in off mode iq off 1 a turn on time t on 10 % to 90 % 300 s turn off time t off 90 % to 10 % 10 ms pull down resistance in off mode r off 100 ? note 1 programmable in 50 mv voltage steps, max output voltage is determined by v dd - dropout voltage. note 2 internal regulator current flowing to ground . 5.12.11 ldocore table 25 : ldo core c haracteristics parameter symbol conditions min typ max unit output v oltage v ddcore i out =0 ma to i max when supplied from v bbat 2.45 2.15 2.5 2.2 2.55 2.25 v decoupling capacitor c in on v dd_ref - 35 % 2.2 +35 % f stabilization capacitor c out i ncluding voltage and temperature coefficient - 55 % 100 +35 % nf esr resistance f > 1 mhz 0.1 ? ? dropout voltage v dropout note 1 50 100 m v note 1 setting v dd_fault_lower 2.65 v avoids ldocore dropout. see section 5.6 for more details ! 5.13 dc/dc b uck c onverters 5.13.1 buckcore table 26 : buckcore c haracteristics parameter symbol conditions min typ max unit input voltage v dd 2.8 note 1 5.0 note 1 v output capacitor c out - 30 % 40 +30 % f output capacitor esr f > 100 khz all caps + track impedance 25 50 m ? inductor value l buck - 30 % 2.2 +30 % h inductor resistance l dcr 100 150 m ? output voltage v bcore i out = i max 0.725 note 2 2.075 v
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 36 of 183 ? 2016 dialog semiconductor parameter symbol conditions min typ max unit output voltage accuracy incl. static line / load regulation - 3 note 3 +3 % output voltage ripple i out = i max 10 mv load regulation transient vtr load i out = 0 ma / 500 ma, di/dt = 50 ma/s 15 30 mv line regulation transient vtr line v dd = 3.0 v . to 3.6 v i out = 500 ma t r =t f =10 s 3 8 mv output current i max 2000 note 4 ma current limit (programmable) i lim buckcore_ilim= 00 - 20 % 1600 20 % ma buckcore_ilim= 01 - 20 % 2000 20 % ma buckcore_ilim= 10 - 20 % 2400 20 % ma buckcore_ilim= 11 - 20 % 3000 20 % ma quiescent current in off mode iq ff 1 a quiescent current in synchronous rectification mode iq on open loop note 5 4.0 ma switching frequency f 2 mhz switching duty cycle d 10 90 % turn on time t on 2.2 ms output pull down resistor @ v out = 0.5 v, can be switched off via core_pd_dis 200 ? efficiency i out =30 ma to i max v dd < 4.2 v 85 90 % on resistance pmos r pmos incl. pin and routing 0.22 0.3 ? on resistance nmos r nmos incl. pin and routing 0.2 ? pfm m ode output voltage v bcore i out < 70 ma 0.5 note 6 2.075 v typical mode switching current 100 ma output current i out 180 ma current limit i lim - 20 % 400 +30 % ma quiescent current in pfm mode iq pfm i out = 0 ma 50 70 a
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 37 of 183 ? 2016 dialog semiconductor parameter symbol conditions min typ max unit frequency of operation 0 5 mhz efficiency i out = 10 ma to 140 ma v dd < 4.2 v 80 % mode transition time 16 18 s note 1 must be in the range of v ddout +/ - 0.3 v . note 2 programmable in 25 mv increments with micro voltage ramp step size of 6.25 mv/ s while slewing . note 3 minimum tolerance is +/ - 30 mv . note 4 buckcore requires >1 v between v dd and v bcore . this ratio depends on l dcr and routing impedances. note 5 quiescent current measurement in open loop synchronous mode. in closed loop configuration, switching losses at iload = 0 will also increase iq on . note 6 m ax. v dd C 1.0 v . 5.13.2 buckpro table 27 : buckpro c haracteristics parameter symbol conditions min typ max unit input voltage v dd 2.8 note 1 5.0 note 1 v output capacitor c out - 30 % 20 +30 % f output capacitor esr f > 100 khz all caps + track impedance 25 50 m ? inductor value l buck - 30 % 2.2 +30 % h inductor resistance l dcr 100 150 m ? output voltage v bpro i out = i max, 0.725 note 2 2.075 v output voltage accuracy incl. static line / load regulation - 3 note 3 +3 % output voltage ripple i out = i max 10 mv load regulation transient vtr load i out = 0 ma / 500 ma, di/dt = 50 ma/s 15 30 mv line regulation transient vtr line v dd = 3.0 v . to .3.6v i out = 500 ma t r =t f =10 s 3 8 mv output current i max 1000 note 4 ma current limit (programmable) i lim buckpro_ilim=00 - 20 % 20 % ma buckpro_ilim=01 - 20 % 20 % ma buckpro_ilim=10 - 20 % 20 % ma buckpro_ilim=11 - 20 % 20 % ma
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 38 of 183 ? 2016 dialog semiconductor parameter symbol conditions min typ max unit quiescent current in off mode iq ff 1 a quiescent current in synchronous rectification mode iq on 2.5 ma switching frequency f 2 mhz switching duty cycle d 10 90 % turn on time t on open loop note 5 2.2 ms output pull down resistor @ v out = 0. 5v, can be switched off via pro_pd_dis 200 ? efficiency i out =30 ma to i max v dd <4.2 v 85 % on resistance pmos r pmos incl. pin and routing 0.33 0.46 ? on resistance nmos r nmos incl. pin and routing 0.3 ? pfm m ode output voltage v bpro i out < 70 ma 0.5 note 6 2.075 v typical mode switching current 50 ma output current i out 90 ma current limit i lim - 20 % 200 +30 % ma quiescent current in pfm mode iq pfm i out = 0 ma 25 45 a frequency of operation 0 5 mhz efficiency i out = 10 ma to 90 ma v dd < 4.2 v 80 % mode transition time 16 18 s note 1 must be in the range of v ddout +/ - 0.3 v . note 2 programmable in 25 mv increments with micro voltage ramp step size of 6.25 mv/ s while slewing . note 3 minimum tolerance is +/ - 30 mv . note 4 buckpro requires >1 v between v dd and v bpro . this ratio depends on l dcr and routing impedances. note 5 quiescent current measurement in open loop synchronous mode. in closed loop configuration, switching losses at iload = 0 will als o increase iq on . note 6 m ax. v dd C 1.0 v .
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 39 of 183 ? 2016 dialog semiconductor 5.13.3 buckmem table 28 : buckmem c haracteristics parameter symbol conditions min typ max unit input voltage v dd 2.8 note 1 5.0 note 1 v output capacitor c out - 30 % 20 +30 % f output capacitor esr f > 100 khz all caps + track impedance 25 50 m ? inductor value l buck - 30 % 2.2 +30 % h inductor resistance l dcr 100 150 m ? output voltage v bmem i out = i max 0.95 note 2 2.525 v output voltage accuracy incl. static line / load regulation - 3 note 3 +3 % output voltage ripple i out = i max 10 mv load regulation transient vtr load i out = 0 ma / 5 00 ma, di/dt = 30 ma/s 20 40 mv line regulation transient vtr line v dd = 3.0 v . to .3.6 v i out = 5 00 ma t r =t f =10 s 5 10 mv output current i max 1000 note 4 ma current limit (programmable) i lim buckmem_ilim=00 - 20 % 800 20 % ma buckmem_ilim=01 - 20 % 1000 20 % ma buckmem_ilim=10 - 20 % 1200 20 % ma buckmem_ilim=11 - 20 % 1500 20 % ma quiescent current in off mode iq ff 1 a quiescent current in synchronous rectification mode iq on open loop note 5 2.5 ma switching frequency f 2 mhz switching duty cycle d 10 90 % turn on time t on 2.2 ms output pull down resistor @ v out = 0.5 v, can be switched off via mem_pd_dis 200 ? efficiency i out =30 ma to i max v dd <4.2 v 85 % on resistance pmos r pmos incl. pin and routing 0.33 0.46 ?
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 40 of 183 ? 2016 dialog semiconductor parameter symbol conditions min typ max unit on resistance nmos r nmos incl. pin and routing 0.3 ? pfm m ode typical mode switching current 50 ma output current i out 90 ma current limit i lim - 20 % 200 +30 % ma quiescent current in pfm mode iq pfm i out = 0 25 45 a frequency of operation 0 5 mhz efficiency i out = 10 ma to 90 ma v dd < 4.2 v 80 % mode transition time 16 18 s vmem_sw switch ron vbmem=1.8 v vdrop=200 mv 0.65 vmem_sw switch turn on time vbmem=1.8 v cload=10 f max 200 400 s vmem_sw switch rpull - down vbmem=1.8 v vout=100 mv 200 note 1 must be in the range of v ddout +/ - 0.3 v . note 2 programmable in 25 mv increments with micro voltage ramp step size of 6.25 mv/us while slewing . note 3 minimum tolerance is +/ - 35 mv . note 4 buckmem requires > 1 v between v dd and v bmem . this ratio depends on l dcr and routing impedances. note 5 quiescent current measurement in open loop synchronous mode. in closed loop configuration, switching losses at iload = 0 will also increase iq on . 5.13.4 buckperi table 29 : buckperi c haracteristics parameter symbol conditions min typ max unit input voltage v dd 2.8 note 1 5.0 note 1 v output capacitor c out - 30 % 20 +30 % f output capacitor esr f > 100 khz all caps + track impedance 25 50 m ? inductor value l buck - 30 % 2.2 +30 % h inductor resistance l dcr 100 150 m ? output voltage v bperi 0.95 note 2 2.525 v output voltage accuracy incl. static line / load - 3 note 3 +3 %
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 41 of 183 ? 2016 dialog semiconductor parameter symbol conditions min typ max unit regulation output voltage ripple i out = i max 10 mv load regulation transient vtr load i out = 0 ma / 500 ma, di/dt = 50 ma/s 20 40 mv line regulation transient vtr line vdd = 3.0 v to 3.6 v i out = 500 ma t r =t f =10 s 5 10 mv output current i max 1000 note 4 ma current limit (programmable) i lim buckperi_ilim=00 - 20 % 800 20 % ma buckperi_ilim=01 - 20 % 1000 20 % ma buckperi_ilim=10 - 20 % 1200 20 % ma buckperi_ilim=11 - 20 % 1500 20 % ma quiescent current in off mode iq ff 1 a quiescent current in synchronous rectification mode iq on open loop note 5 2.5 ma switching frequency f 2 mhz switching duty cycle d 20 90 % turn on time t on 2.2 ms output pull down resistor @ v out = 0.5 v 200 ? efficiency i out < i max v dd < 4.2 v 80 85 % on resistance pmos r pmos incl. pin and routing 0.33 0.46 ? on resistance nmos r nmos incl. pin and routing 0.3 ? pfm m ode typical mode switching current 50 ma output current i out 90 ma current limit i lim - 20 % 200 +30 % ma quiescent current in pfm mode iq pfm i out = 0 25 45 a frequency of operation 0 5 mhz efficiency i out = 10 ma to 90 ma v dd < 4.2 v 80 % mode transition time 16 18 s vperi_sw switch v bperi = 1.8 v 0.65
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 42 of 183 ? 2016 dialog semiconductor parameter symbol conditions min typ max unit ron vdrop=200 mv vperi_sw switch turn on time v bperi = 1.8 v cload=10 f max 200 400 s vperi_sw switch rpull - down vbperi = 1.8 v vout=100 mv 200 note 1 must be in the range of v ddout +/ - 0.3 v . note 2 pr ogrammable in 25 mv increments . note 3 minimum tolerance is +/ - 35 mv . note 4 buckperi requires >1 v between v dd and v bperi . this ratio depends on l dcr and routing impedances . note 5 quiescent current measurement in open loop synchronous mode. in closed loop configuration, switching losses at iload = 0 will also increase iq on .
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 43 of 183 ? 2016 dialog semiconductor 5.14 battery charger 5.14.1 charger s upply m odes table 30 : charger s upply m ode c haracteristics supply mode symbol conditions min typ max unit vbus (low - power usb, 100 ma) vbus upstream port voltage with 500 m ? impedance 4.4 5.5 v iset_usb<3:0> 10 ma steps 80 120 ma vbus (high - power usb, 500 ma) vbus upstream port voltage with 500 m ? impedance 4.75 5.5 v iset_usb<3:0> 50 ma steps 400 600 ma vbus (dchg usb, 2000 ma) vbus upstream port voltage with 200 m ? impedance 4.5 5.5 v iset_usb<3:0> 200 ma steps 600 1800 ma dcin (wall brick, 2000 ma) vdcin as vbus, higher currents can require higher voltages 4.4 5.5 v iset_dcin<3:0> 10 ma, 50 ma and 200 ma steps 80 1800 ma 5.14.2 charger b uck table 31 : charger b uck c haracteristics parameter symbol conditions min typ max unit input voltage v center 4.4 5.6 v output capacitor c out 30 f esr of output capacitor f > 100 khz 20 m inductor value l buck - 30 % 2.2 to 4.7 +30 % h inductor resistance l dcr f = 1 mhz 100 m output voltage v ddout i out = 1000 ma included static load regulation 3.6 v bat + 250 mv v ripple voltage i out = 1000 ma l buck = 4.7 h 10 mv static load regulation v s load i out = 1 ma to 1000 ma 55 80 mv load regulation transient vtr load i out : 0 ma / 1000 ma, di/dt = 20 ma/s 45 65 mv line regulation transient vtr line vbus_prot=4.4 v to 5.6 v i out =1000 ma t r = t f = 10 s 10 mv output current i max 1890 ma
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 44 of 183 ? 2016 dialog semiconductor parameter symbol conditions min typ max unit current limitation i lim 2 - wire programmable 10 ma, 50 ma and 200 ma steps 70 1800 ma quiescent current in off mode 1 a quiescent current in synchronous rectification mode 5 ma f_buck f requency of operation 2 mhz switching duty cycle 10 100 % ton t urn on time 2.2 ms efficiency i out = 1000 ma vbus_prot = 5 v 85 90 % r_pmos pmos on resistance including pin and routing 0.08 0.15 0.2 r_nmos nmos on resistance including pin and routing 0.15 0.25 0.3 r_vbus_prot internal switch on resistance including pin and routing, vbus_prot= 4.8 v 0.05 0.1 0.2 s leep m ode C pfm mode sleep mode output current i outsleep 100 ma current limitation 75 278 300 ma iq_ sleep C no load supply current in sleep mode i out = 0 ma 80 100 a f_buck frequency of operation 0 5 mhz efficiency i out = 10 ma to 100 ma 90 % efficiency i out = 1 ma to 50 ma v dd =4.8 v 80 % mode transition time 16 18 s 5.14.3 voltage l evels on vbat table 32 : voltage l evels on vbat parameter symbol conditions min typ max unit bat_fault 2. 8 v battery voltage range v bat 2.8 4.425 v
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 45 of 183 ? 2016 dialog semiconductor parameter symbol conditions min typ max unit ichg_bat v bat < bat_fault 20 40 60 ma 5.14.4 charging m odes table 33 : charging m odes parameter symbol conditions min typ max unit cc mode output current 6 bits ichg_bat (30 ma step s) 0 300 1890 ma cc absolute accuracy ichg_bat < 100 ma - 10 +10 ma cc absolute accuracy ichg_bat > 100 ma - 10 +10 % cv mode output voltage vchg_bat (25 mv steps) 3.65 4.2 4.425 v cv output voltage accuracy vchg_bat - 25 25 mv 5.14.5 charger d etection c ircuit table 34 : charger d etection c ircuit parameter symbol conditions min typ max unit charger detect threshold vch_det vchg_bat < 4.2 v 4.25 4.35 4.4 v vchg_bat > 4.2 v 4.45 4.55 4.6 v charger current limit reduction threshold vch_thr (configurable) 3.8 4.4 4.8 v charger insertion debounce time 10 ms vbus, dcin excess voltage threshold 5.4 5.6 5.8 v 5.14.6 vbus c harge c ontrol table 35 : vbus c harge c ontrol parameter symbol conditions min typ max unit data s ource v oltage v dat_src @i dat_src 0 . 5 0 . 7 v data s ource cu rrent i dat_src 0 200 a data d etect v oltage v dat_ref @i dat_sink 0 . 25 0 . 4 v data s ink c urrent i dat_sink 50 150 a d+ source on time t dp_src_on 100 ms d+ source off to high current t dpsrc_hicrnt 40 ms vbus load in low - power s uspend m ode i vbus_suspend 0 v vbus 5.25 v t avg = <1 s, no spikes higher than 100 ma 500 a
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 46 of 183 ? 2016 dialog semiconductor 5.14.7 c harge t imer table 36 : charge t imer parameter register conditions min step max step total c harging t imer setting tctr 30 min t otal . c harge time is defined as the total charge time from when the charger was enabled (both for linear and pre - charge mode charging). if the timer expires, the chg_to flag is set in the event register, an irq issued and the charging is disabled. se tting the tctr to 0x00 disables the timer. 0 30 450 min read back of current timer value chg_time this register can be used to read back the current value of the charge time counter, counting down from the value loaded by the tctr 0 2 510 min 5.14.8 dccc and a ctive - d iode table 37 : dccc and a ctive d iode parameter symbol conditions min typ max unit active d iode r on v bat = 3.6 v , i = 500 ma including pin and routing 0.14 circuit a ctivation v oltage v bat - v ddout 10 20 40 mv maximum diode current id max 2.2 a 5.14.9 backup b attery c harger table 38 : backup b attery c harger parameter symbol condition min typ max unit backup b attery c harging c urrent bcharger_is et v in = 3.6 v, v bbat = 2.5 v 100 n ote 1 6000 a charger t ermination v oltage bcharger_v set v in = 3.6 v 1.1 3.1 v backup b attery s hort c ircuit c urrent v bbat = 0 v 9 ma stabilizationcapacitor c out 55 % 470 +35 % nf esr of capacitor f > 1 mhz 0.1 ? dropout voltage v dropout i out = 5 ma 150 200 mv quiescent c urrent iq i out > 50 a 5.25 + 1.75 % of i out a i out < 50 a 5.25 + 1.5 % of i out a
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 47 of 183 ? 2016 dialog semiconductor note 1 programmable in 100 a increments from 100 a to 1000 a and 1 ma increments from 1 ma to 6 ma . 5.14.10 boost c onverter table 39 : boost c onverter p arameters measured u sing external components shown in conditions. parameter symbol conditions min typ max unit output v oltage v boost 2.8 v < v in < 4.5 v 0.03 ma < i load <50 ma 4.6 25 v efficiency 1 mhz, v boost = 20 v i load = 50 ma; 80 % output v oltage r ipple i load = 26 ma c out = 2 out ) 200 mv p - p operating q uiescent current i load = 0 ma; automatically changed to discontinuous mode 250 350 a a boost ceramic capacitor recommended; figure w ith 25 v voltage bias, may correspond to 10 f nom. value without bias 1 2 f boost f > 100 khz 100 m ? ? note 1 for reduced backlight power requirements a lower current limitation of 710 ma can be selected via control boost_ilim .
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 48 of 183 ? 2016 dialog semiconductor 5.14.11 wled d river table 40 : wled d river parameter conditions min typ max unit absolute output current accuracy (led1_in1 / led2_in / led3_in) full scale tolerance - 20 +20 % linearity 1 ma to 26 ma - 10 +10 linearity 0.1 ma to 1 ma - 20 +20 relative output current accuracy (iout1 - iout2 ) / (iout1 + iout2) i out 1/2/3 = 5 ma to. 2 6 ma i out 1/2/3 = < 5 ma - 3.25 - 4.5 +3.25 +4.5 % current sink vdsat @ i out = 2 6 ma 0.6 v led current sink vdmax max. voltage drop at current source 5.5 v ramp step rate tstep - up 1 ms idac step size ledx_current = 0 to 255 0.212 db 5.15 adc table 41 : adc parameter symbol conditions min typ max unit adc reference voltage v ddcore / tsiref 1.8 note 1 2.5 2.6 v off current 1 a adc operating current during conversion 100 a adc resolution 10 bit adc integral non linearity 2 lsb adc differential non linearity 0.8 lsb adc absolute accuracy 12 15 mv adc conversion clock 1.0 mhz auto - zero time 5 s conversion time 29 s total adc conversion time 34 s internal mux - resistance r int 5 k ? maximum source impedance r source note 2 100 k ? internal sampling capacitor. 10 pf
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 49 of 183 ? 2016 dialog semiconductor parameter symbol conditions min typ max unit acquisition time 10 12 14 s input c apacitance c int total input capacitance 10.5 pf vddout voltage range channel 0 v ddout - v ddcore gain of 1.25 adc = [(v ddout - 2.5 v)*0.5] *1023 2.5 4.5 v ich current measurement using an internal current mirror device. channel 1, used for dynamic safety timer and eoc detection equivalent to 3.9 ma/bit 0 1000 ma tbat voltage range channel 2 voltage across a ntc resistor in the battery pack, 50 a biasing 0 vddcore v vbat voltage range channel 3 v bat - v ddcore gain of 1.25 adc = [(v bat - 2.5 v)*0.5] * 1023 2.5 4.5 v adcin4 C 6 voltage range channel 4 C 6 adc = [v in /2.5 v] * 1023 0 2.5 v vbbat voltage range channel 9 gain of 0.5 adc = [(v bbat /2.5 v)*0.5] * 1023 0 5.0 v adcin4 current source channel 4 if enabled 15 a adcin5 comparator threshold channel 5 disabled during adcin5 conversion 1.2 v ron, tsi x - y switches 5 ? mux cross talk isolation 60 db note 1 tsiref voltage range . note 2 r source is the impedance of the external source the adc is sampling.
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 50 of 183 ? 2016 dialog semiconductor 6 accessory i dentity d etection (acc_id_det) this block detects the status of the acc_id_det pin. it is capable of detecting three different states: floating (usb peripheral device connected) shorted to ground (usb host device connected) connected to ground via resistor (accessory asserted) figu re 5 : id d etection c ircuitry the sensing can be turned on/off id_float and id_gnd asserts an interrupt at both (rising and falling) edges. the sensing can be debounced. if a m ini - usb or an accessory is connected to the acc_id_det pin in power - down mode a wake - up will be initiated (only at falling edge of id_float). if the accessory coding requires the detection of an impedance less than 40 k? an external resistor has to be placed between vddcore and acc_id_det. 6.1 accessory d etection s tates table 42 : accessory d etection s tates external r esistance to gnd acc_id_det s tate id_float id_gnd r > 160 k ? floating open pin. usb b - device connected (peripheral) high low 40 k ? < r < 160 k ? high via resistor to ground. accessory connected low low r < 40 k ? low < 10 ? to ground. usb a - device connected (host) low high v d d c o r e a c c _ i d _ d e t i d _ g n d i d _ f l o a t + - + - 1 2 . 5 u a 2 . 0 v 0 . 5 v
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 51 of 183 ? 2016 dialog semiconductor r eal time c lock and 32 khz o scillator the rtc block keeps track of the rtc clock counter and alarm function. the rtc block will operate from the ldocore power supply. 6.2 32 khz o scillator the clock oscillator cell is used to drive the real time clock (rtc) counter. it works with an external pie zoelectric oscillator crystal at 32.768 khz. in order to achieve typically the desired crystal frequency an external capacitor (10 pf to 20 pf, depending on the parasitic capacitance of the board) is connected to ground from each of the crystal pins. the start - up time of the oscillator is typically 0.5 s over the voltage range. when the crystal is not mounted the xtal pins should be grounded. the 32 khz clock signal is made available at the out_32k pin and the buffer can be disabled from the sequencer duri ng power - down mode. the timekeeping error from the frequency variance of crystal oscillators (typ. +/ - 20 ppm) can be trimmed individually by +/ - 242 ppm with a resolution of 1.9 ppm (1/(32768 x 16)). the timekeeping correction will be applied only towards the on - chip rtc block. to avoid potential clock jitter issues , the 32 khz clock signal at the out_32k pin provides the original frequency of the crystal. note the oscillator inputs will be able to withstand a leakage current, corresponding to at least a 10 m? connected between the pin and any signal level between v ddout and gnd. 6.3 rtc c ounter and a larm the rtc counter will count the number of 32 khz clock periods, providing a sec onds , min utes , h ou rs, day , month and year output. year 0 corresponds to 2000 , the maximum is 63 years. the value of the rtc calendar shall be read - /write - able via the power manager communication. the calendar is reset to zero when vddcore is lost. there is an alarm register containing min utes , h ou rs, day, month, and year. when th e rtc counter register value corresponds to the value set in the alarm an irq event will be triggered ( and a wake - up if da9053 is in power - down m ode ) . the trigger will also set a bit in an event register to notify that an alarm has occurred. the alarm can alternatively be asserted from a periodic tick signal that, depending on control tick_ type , is either asserted every second or minute. in the case where the host has enabled both alarms it can be determine d from the status of alarm_ type whether the irq/wak e - up was caused by the timer or the tick. the power manager registers alarm_on and tick_on enable/disable the alarm/tick. the power manager register bit monitor will be set to 0 each time the rtc is powered up. software shall set this bit to 1 when sett ing the time and date, which will allow software to detect a subsequent loss of the clock. note values written into the rtc calendar and alarm registers have to be valid regarding the allowed value range (see register description, for example maximum 60 for seconds or minutes). the rtc seconds registers define a 32 - bit seconds counter (approx. 136 years), that can only be reset via the npor and starts counting seconds after npor is released. using the rtc input clock the output port s gpo10 an d gpo11 can be toggled with a configurable periodic pulse. in this mode gpo10 or gpo11 offer blinking led drivers that are able to run in power - down m ode .
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 52 of 183 ? 2016 dialog semiconductor figure 6 : sch ematic of the rtc o scillator and c ounter f unctionality 6.4 oscillator table 43 : lpi i nterface s ignals parameter symbol conditions min typ max unit supply voltage v ddcore 2.0 2.5 2.55 v oscillator crystal frequency f osc 32.768 khz crystal series resistance r osc 100 k ? output frequency f out 32.768 khz start - up time for cell over the voltage range t start 0.5 2.0 s current consumption power down mode 1 5 a current consumption active mode 3 5 a input duty cycle d xtal1 bypass mode 40 50 60 % out_32k clock jitter c ycle to cycle 20 30 ns 32 . 768 khz crystal x in x out comparator alarm 32 k _ osc internal clock power manger register ( r / w ) rtc calendar counter power manger register ( r / w ) alarm register alarm _ on q q set clr s r vdd core register write vdd core vdd core vdd core vdd core q q set clr s r vdd core monitor monitor npor vdd core c 32 k c 32 k
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 53 of 183 ? 2016 dialog semiconductor 7 id c ode/ s cratch p ad da9053 offers 10 general purpose registers, which can be configured from otp cells. the otp cells can be programmed during test/production with an individual code and so can provide a device specific serial number as required for music and media applications supporting digital rights management (drm) . the general purpose registers are loaded from otp when da9053 starts - up from reset - m ode and can be read only protected during fusing. if writing is enabled th e registers can be used by the application to store up to 10 bytes of data that a host processor can use (for example after powering up from low - power modes ) . 7.1 programming the id c ode/ s cratch p ad the id c ode/ s cratch pad otp cells can be programmed only once and cannot be erased. programming can only take place when all of the following conditions are satisfied: da9053 is in power commander mode . da9053 has reached the active mode operational state . there is no charger attached . the supply voltage for the pro gramming vpp has been provided at the vbus node . the range modifiers have been set to select the correct addresses (otp_gp = 1) . the write access enable bit gp_write_dis has been set to program the intended gp register mode (after being programmed once to read only registers r133 - r142 can only be written for fusing). the content received from a read can no longer be modified just by writing in to the registers. the lock bit in the otp is in the correct state (otp_gp_lock = 0) . note connecting tp to vddcore enables the power commander mode . the data intended to be programmed into the otp must be first loaded into the related gp_id registers using the hs 2 - wire interface. the contents of the gp_id registers are then transferred into t he otp cells by setting otp_transfer = otp_rp = 1. once started the transfer cannot be stopped. during an ongoing programming transfer the device will not react to any external events that otherwise would make it transition to other states. upon completion of a transfer the otp_transfer bit will be reset automatically. so the end of the transfer can be determined by polling this bit. if the lock bit otp_gp_lock is set any further programming of the id c ode/ s cratch pad is suppressed. if the write access cont rol bit gp_write_dis is set, then the gp_id registers become read - only (reading content will be always a 100 % mirror of the related otp cells). in a production environment it is mandatory to check the success of the programming of the gp_id registers by reading back the otp contents. da9053 defaults to performing a margin mode read which allows the reliability of the stored information to be assessed. to initiate a read transfer from the otp cells into the related gp_id registers, firstly set otp_gp = 1 to access the correct addresses, and then otp_rp = 0 and otp_transfer = 1 to start the read operation. read transfers are unaffected by the state of the lock or write enable bits .
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 54 of 183 ? 2016 dialog semiconductor 8 typical c haracteristics 8.1 buck r egulator p erformance the following performance was measured while using 2.2 h inductors : figure 7 : buckperi e fficiency c urves figure 8 : buckcore e fficiency c urves figure 9 : buckpro e fficiency c urves figure 10 : buckmem e fficiency c urves figure 11 : buckpro l oad r egulation t ransient vout = 1.2 v, iload = 500 ma. figure 12 : buckpro l ine r egulation t ransient vbuck = 1.35 v, il oad = 500 ma, vsupply = 3 v
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 55 of 183 ? 2016 dialog semiconductor 8.2 linear r egulator p erformance figure 13 : typical ldo l oad r egulation figure 14 : typical ldo d rop - o ut v oltage figure 15 : typical ldo l ine t ransient transition of 3.6 v to 4.2 v at vbat figure 16 : ldo l oad t ransient (1 ma to imax of 40 ma) vldo = 1.2 v ldo load regulations 1.98 1.99 2 2.01 2.02 2.03 2.04 0 0.1 0.2 0.3 0.4 0.5 0.6 output current (a) output voltage (v) 1.16 1.17 1.18 1.19 1.2 1.21 1.22 ldo3 ldo4 ldo5 ldo6 ldo7 ldo8 ldo9 ldo10 ldo1 ldo2 ldo3 dropout voltage vs load current (using test mux) 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1 0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2 load current (a) dropout voltage (v)
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 56 of 183 ? 2016 dialog semiconductor 8.3 typical ldo v oltage vs t emperature figure 17 : typical ldo v oltage vs t emperature 8.4 adc p erformance figure 18 : adc dnl p erformance figure 19 : adc inl p erformance
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 57 of 183 ? 2016 dialog semiconductor 8.5 power p ath p erformance figure 20 : power p ath b ehaviour usb 100 m ode figure 21 : power p ath b ehaviour usb 500 m ode figure 20 and figure 21 and show increasing load current supplied from v bus , powerpath loop red uces ich until active diode turns on which then allows current from battery to supply system load current via vdd_out. figure 22 : transitioning s upply from vchg (via dcin) to vbat top trace = vddout, bottom tra ce = dcin figure 23 : transitioning s upply from usb 5 v (via vbus) to vbat top trace = vddout, bottom trace = vbus
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 58 of 183 ? 2016 dialog semiconductor 8.6 boost and led c urrent c ontrol p erformance figure 24 : wled c urrent p erformance figure 25 : wled r elative a ccuracy figure 26 : boost c onverter e fficiency c urves figure 27 : boost r egulation v oltages boost efficiency vs load current 0.00% 10.00% 20.00% 30.00% 40.00% 50.00% 60.00% 70.00% 80.00% 90.00% 100.00% 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 load (a) efficiency (%) vbat = 3.2v, 1mhz boost frequency vbat = 3.2v, 2mhz boost frequency vbat = 4.2v, 1mhz boost frequency vbat = 4.2v, 2mhz boost frequency boost current limit 12 12.5 13 13.5 14 14.5 15 15.5 0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 load (a) output voltage (v) vbat=3.2v, 1mhz boost frequency vbat=3.2v, 2mhz boost frequency vbat=4.2v, 1mhz boost frequency vbat=4.2v, 2mhz boost frequency
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 59 of 183 ? 2016 dialog semiconductor 9 functional d escription figure 28 : control p orts and i nterface 9.1 power m anager io p orts the power manager input ports are supplied either from the internal rail vddcore or vdd_io2. the output ports are supplied from vdd_io1 or vdd_io2. all output ports are push - pull type except nreset, nirq and nvdd_fault. 9.2 on/off and hw - w atchdog p ort (nonkey/keep_act) the nonkey signal is an edge triggered high to low wake - up interrupt/event intended to switch - on the da9053 supplied application. nonkey is always enabled during power - down mode, so that the application can be switched - on with a disabled gpio extender. the wake - up event can be disabled via the interrupt mask. this pin can be alternatively asserted to the watchdog unit, s o that every assertion of the pin (rising edge sensitive) sets its bit similar to a write via the power manager bus. the host has to release keep_act in advance to the next assertion during continuous watchdog supervision (if enabled). the minimum assertio n and de - assertion cycle time is 150 s. 9.3 hardware r eset (nshutdown, nonkey, gpio14 & gpio15) a user - initiated hard reset at the da9053 nshutdown is an active low input initiated typically by a push button switch or an asserted error detection line from a host processor. the sequencer then powers down all domains in reverse order down to step 0 and all supplies of da9053 except ldocore are switched off. da9053 includes a second hardware reset that follows the nonkey after being asserted for a period of 5 s 30 %. the same can be achieved by a parallel connection of gpi14 and gpi15 to ground for 5 s 30 %. if the watchdog has been disabled, this feature provides the ability to emergency turn - off the application in the event of a software lock - up without the need for a dedicated reset hardware switch or removing the battery. after a minimum time - out of 500 ms da9053 will start to power up again. it will wait for a valid w ake - up event ( for example key press) or will start the power sequencer automatically if autoboot is enabled. by asserting ext_wakeup it can request the host processor to control the subsequent start - up. alternatively the power up sequence can be performed autonomously by the pmic following otp pre - configurations. a detection of a hard reset forces the assertion of nreset to low when the sequencer returns from power - down m ode to reset m ode. this type of reset is typically used d a 9 0 5 3 h o s t p r o c e s s o r n i r q n o n k e y n r e s e t v d d v b u s d c i n n s h u t d o w n g p i o _ 0 . . . 1 5 o u t _ 3 2 k c o n t r o l i f p w r _ u p s y s _ u p
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 60 of 183 ? 2016 dialog semiconductor only for severe and unrecoverable hardware or software p roblems, because it completely resets the processor and can result in data loss. 9.4 reset o utput (nreset) the nreset signal is an active - low output signal from da9053 to the host processor, which tells the host to enter the hardware - reset state. nreset is alw ays asserted at the beginning of a da9053 cold start from no - power m ode to when the da9053 returns to reset m ode. nreset can also be asserted as a soft reset after the sequencer finishes powering down without progressing to reset m ode. the reset timer trig ger signal can be configured to be ext_wakeup, sys_up or pwr1_up. after being asserted nreset remains low until the reset timer is started from the selected trigger signal and expires. the expiry time can be configured from 1 ms to 1024 ms. 9.5 accessory and i d d etect (acc_id_det) in active and power - down mode s the detector can track the condition of the usb id line and differentiates between the following three conditions: acc_id_det: floating (usb peripheral device connected) shorted to ground (usb host devi ce connected) connected to ground via resistor (accessory asserted) if the acc_id_det pin stops floating (falling edge) during power - down m ode a wake up is triggered. 9.6 system e nable (sys_en) sys_en is an input signal from the host processor to da9053 which initiates enabling the system power supplies. the control sys_en will be initialized from otp if the related port is configured as gpi or gpo. the register bit sys_en can be read and changed via the control interfaces. da9053 will not accept any power mod e transition commands until the sequencer has stopped processing ids. de - asserting sys_en informs the da9053 that the host processor is going into a standby/hibernate mode. when the port is changing from active to passive state there is no irq or wake - up e vent trigger. with the exception of supplies that are configured in active m ode with a voltage preset before powering down all regulators and buck converters in power domain power1, power and system will be sequentially disabled in reverse order. 9.7 power e na ble (pwr_en) pwr_en is an input signal from the host processor to da9053 or is configured via otp or host commands. initialisation, irq assertion and register bit pwr_en control is similar to sys_en. to ensure the correct sequencing sys_en has to be active before asserting pwr_en. when de - asserting sys_en the sequencer will sequentially power down power1, power and system domains respectively. 9.8 power1 e nable (pwr1_en) pwr1_en is an input signal from a host to da9053 and is configured via otp or host commands . initialisation, irq assertion and register bit pwr1_en control is similar to sys_en. the domain power1 is a sub power domain for general purpose.
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 61 of 183 ? 2016 dialog semiconductor 9.9 general p urpose f eedback s ignal 1 (gp_fb1: ext_wakeup/ready) the feedback gp_fb1 supports two different mode s. if configured as ext_wakeup it is an active high output signal to the host processor that indicates a valid wake - up event during power - down m ode. external signals that are causing wake - up events are debounced before da9053 assert the ext_wakeup signal. ext_wakeup is released when entering the active m ode. if configured as ready signal it indicates ongoing dvc or power sequencer activities. the signal is active low and is asserted from da9053 as long as the power sequencer processes ids or dvc voltage tra nsitions are ongoing. 9.10 power d omain s tatus (sys_up, pwr_up/gp_fb2) the power domain status indicators are active high and assigned after the sequencer has processed all ids of a power domain (all assigned supplies are up). when domains are disabled during power mode transitions the status indicator is released before the da9053 sequencer processes the last step of a domain. pwr_up is one mode of the general purpose indicator gp_fb2 that can also be used as a configurable feedback signal that is level/time c ontrolled from the power sequencer. 9.11 supply r ail f ault (nvdd_fault) nvdd_fault is an active low output signal to the host processor to indicate a vddout low status. the assertion of nvdd_fault indicates that the main battery and the supply input voltage is low and therefore informs the host processor that the power will shut down ve ry soon. after that the processor may operate for a limited time from the backup battery, which can provide power to the processor for a few cycles. in the event of nvdd_fault assertion the processor may be programmed to enter an emergency mode, for exampl e external memory data refresh is no longer performed. 9.12 interrupt r equest (nirq) the nirq is an active low output signal which indicates that an interrupt causing event has occurred and that the event and status information is available in the related regis ters. such information can be temperature and voltage of the pmic, fault conditions, charging status, status changes at gpi ports, and others . the event registers hold information about the events that have occurred. events are triggered by a status change at the monitored signals. when an event bit is set the nirq signal is asserted (unless this interrupt is masked by a bit in the irq mask register). the nirq will not be released until the event registers have been cleared. 9.13 real t ime c lock o utput (out_32k) the out_32k is an output signal that generates a buffered signal of the da9053 32 khz oscillator. the 32 khz oscillator will always run on the da9053 following the initial start - up from no - power m ode until the device has reached no - power m ode again. the signal output buffer can be disabled during power - down mode. 9.14 io s upply v oltage (vdd_io1 and vdd_io2) vdd_io1 and vdd_io2 are two independent io supply rail inputs of da9053 that can be individually assigned to the power manager interface, power manager ios and gpios. the rail assignment determines the io voltage levels and logical thresholds . the selection of the supply rail for gpios is also partially used for their alternate functions. gpos configured in open drain mode have to use the vdd_io1 rail if an internal pull - up resistor is required.
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 62 of 183 ? 2016 dialog semiconductor 10 control i nterfaces the da9053 is completely software controlled from the host by registers. da9053 offers two independent serial control interfaces to access these registers. the communication via the main power man ager interface is selectable to be either a 2 - wire or a 4 - wire connection (i 2 c or spi compliant). the alternat iv e interface is fixed towards a 2 - wire bus. data is shifted in to or out from da9053 under the control of the host processor that also provides t he serial clock. 10.1 power m anager i nterface (4 - w ire and 2 - w ire c ontrol b us) this is the dedicated power control interface from the primary host processor. in 4 - wire mode the interface uses a chip - select line (ncs/nss), a clock line (sk), data input (si) and d ata output line (so). 10.2 4 - w ire c ommunication in 4 - wire mode the da9053 register map is split into two pages with each page containing up to 128 registers. the register at address zero on each page is used as a page control register. the default active page a fter reset includes registers r1 to r127. writing to the page control register changes the active page for all subsequent read/write operations. after modifying the active page it is recommended to read back the page control register to ensure that future data exchange is accessing the intended registers. the 4 - wire interface features a half - duplex operation (data can be transmitted and received with in a single 16 - bit frame) at enhanced clock speed (up to 14 mhz). it operates at the provided host clock fr equencies. figure 29 : schematic of a 4 - w ire and 2 - w ire p ower m anager b us a transmission begins when initiated by the host. reading and writing is accomplished by the use of an 8 - bit command, which is sent by the host prior to the exchanged 8 - bit data. the byte from the host begins shifting in on the si pin under the control of the serial clock sk provided from the host. the first seven bits specify the register address (0 to 127, decimal) which will be written or read by the host. the register address is automatically decoded after receiving the seventh address bit. the command word ends with an r/w bit, which specifies the direction of the following data exchange. during register writing the host continues sending out data during the following eight sk clocks. for reading the host stops transmitting and the 8 - bit register is clocked out of da9053 during the consecutive eight sk clocks of the frame. address and data are transmitted with msb first. ncs resets the interface when inact ive and it has to be released between successive cycles. the so output from da9053 is normally in high impedance state and active only during the second half of read cycles. a pull - up or pull - down resistor may be needed at the so line if a floating logic signal can cause unintended current consumption inside other circuits. d a 9 0 5 3 ( s l a v e ) h o s t p r o c e s s o r s k s o s i n c s / n s s n c s / n s s s i s k s o n c s / n s s v d d i o v d d i o v d d i o s l a v e d e v i c e s i s k s o n c s / n s s v d d i o 4 - w i r e i n t e r f a c e h o s t p r o c e s s o r d a 9 0 5 3 p e r i p h e r a l d e v i c e s o s k p e r i p h e r a l d e v i c e s d a s c l s c l s d a v d d i o v d d i o 2 - w i r e i n t e r f a c e
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 63 of 183 ? 2016 dialog semiconductor table 44 : 4 - w ire c lock c onfigurations cpol c lock p olarity cpha c lock p hase output d ata is u pdated at sk e dge input d ata is r egistered at sk e dge 0 (idle low) 0 falling rising 0 (idle low) 1 rising falling 1 (idle high) 0 rising falling 1 (idle high) 1 falling rising the da9053 4 - wire interface offers two further configuration bits. clock polarity (cpol) and clock phase (cpha) define when the interface will latch the serial data bits. cpol determines whether sk idles high (cpol = 1) or low (cpol = 0). cpha determines on which sk edge d ata is shifted in and out. with cpol = 0 and cpha = 0 setting da9053 latches data on the sk rising edge. if the cpha is set to 1 the data is latched on the sk falling edge. cpol and cpha states allow four different combinations of clock polarity and phase; each setting is incompatible with the other three. the host and da9053 must be set to the same cpol and cpha states to communicate with each other. figure 30 : 4 - w ire h ost w rite and r ead t iming (ncs_pol = 0, cpol = 0, cpha = 0) figure 31 : 4 - w ire h ost w rite and r ead t iming (ncs_pol = 0, cpol = 0, cpha = 1) a 0 a 6 a 5 a 4 a 3 a 2 a 1 r / w n d 0 d 6 d 5 d 4 d 3 d 2 d 1 d 7 n c s s k s i s o 4 - w i r e w r i t e a 0 a 6 a 5 a 4 a 3 a 2 a 1 r / w n n c s s k s i s o 4 - w i r e r e a d d 0 d 6 d 5 d 4 d 3 d 2 d 1 d 7 l a t c h d a t a h i - z a 0 a 6 a 5 a 4 a 3 a 2 a 1 r / w n d 0 d 6 d 5 d 4 d 3 d 2 d 1 d 7 n c s s k s i s o 4 - w i r e w r i t e a 0 a 6 a 5 a 4 a 3 a 2 a 1 r / w n n c s s k s i s o 4 - w i r e r e a d d 0 d 6 d 5 d 4 d 3 d 2 d 1 d 7 l a t c h d a t a h i - z
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 64 of 183 ? 2016 dialog semiconductor figure 32 : 4 - w ire h ost w rite and r ead t iming (ncs_pol = 0, cpol = 1, cpha = 0) figure 33 : 4 - w ire h ost w rite and r ead t iming (ncs_pol = 0, cpol = 1, cpha = 1) table 4 : 4 - w ire i nterface s ummary parameter signal l ines ncs chip select si serial input data master out slave in so serial output data master in slave out sk transmission clock interface push - pull with tristate supply voltage selected from vdd_io1/vdd_io2 1.6 v to 3.3 v data rate effective read/write data up to 7 mbps transmission half - duplex msb first 16 - bit cycles 7 - bit address, 1 - bit read/write, 8 - bit data configuration cpol c lock polarity cpha c lock phase ncs_pol ncs is active low/high a 0 a 6 a 5 a 4 a 3 a 2 a 1 r / w n d 0 d 6 d 5 d 4 d 3 d 2 d 1 d 7 n c s s k s i s o 4 - w i r e w r i t e a 0 a 6 a 5 a 4 a 3 a 2 a 1 r / w n n c s s k s i s o 4 - w i r e r e a d d 0 d 6 d 5 d 4 d 3 d 2 d 1 d 7 l a t c h d a t a h i - z a 0 a 6 a 5 a 4 a 3 a 2 a 1 r / w n d 0 d 6 d 5 d 4 d 3 d 2 d 1 d 7 n c s s k s i s o 4 - w i r e w r i t e a 0 a 6 a 5 a 4 a 3 a 2 a 1 r / w n n c s s k s i s o 4 - w i r e r e a d d 0 d 6 d 5 d 4 d 3 d 2 d 1 d 7 l a t c h d a t a h i - z
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 65 of 183 ? 2016 dialog semiconductor note reading the same register at high clock rates directly after writing it does not guarantee a correct value. it is recommended to keep a delay of one frame until re - accessing a register that has just been written ( for example by writing/reading another register address in between). 10.3 2 - w ire c ommunication the power manager interface can be configured for a 2 - wire serial data exchange. it has a configurable slave write address (default: 0x90) and a configurable slave read address (default: 0x91). sk provides the 2 - wire clock and so carries all the power manager bidirectional 2 - wire data. the 2 - wire interface is ope n - drain supporting multiple devices on a single line. the bus lines have to be pulled high by external pull - up resistors (2 k ? to 20 k ? range). the attached devices only drive the bus lines low by connecting them to ground. as a result two devices cannot c onflict, if they drive the bus simultaneously. in standard/fast mode the highest frequency of the bus is 400 khz. the exact frequency can be determined by the application and do es not have any relation to the da9053 internal clock signals. da9053 will foll ow the host clock speed within the described limitations and does not initiate any clock arbitration or slow down. in h igh s peed mode the maximum frequency of the bus may be increased towards 1.7 mhz. this mode is supported if the sk line is driven with a push - pull stage from the host and if the host enables an external 3 ma pull - up at the so pin to decrease the rise time of the data. in this mode the so line on da9053 is able to sink up to 12 ma. in all other respects the high speed mode behaves as the sta ndard/fast mode. communication on the 2 - wire bus always takes place between two devices, one acting as the master and the other as the slave. the da9053 will only operate as a slave. as opposed to the 4 - wire mode the 2 - wire interface has direct (linear) ac cess to the whole da9053 register space (except r0 and r128). this is achieved by using the msb of the 2 - wire 8 - bit register address as a selector of the register page (this does not modify the page control register r0/r128 that is accessible only in 4 - wir e mode). 10.3.1 details of the 2 - w ire c ontrol b us p rotocol all data is transmitted across the 2 - wire bus in groups of 8 bits. to send a bit the so line is driven towards the independent state while the sk is low (a low on so indicates a zero bit). once the so has settled the sk line is brought high and then low. this pulse on sk clocks the so bit into the receiver s shift register. a two byte serial protocol is used containing one byte for address and one byte data. data and address transfer is msb transmitted fi rst for both read and write operations. all transmission begins with the start condition from the master during the bus is in idle state (the bus is free). it is initiated by a high to low transition on the so line while the sk is in the high state (a stop condition is indicated by a low to high transition on the so line while the sk is in the high state). figure 34 : timing of 2 - w ire start and stop c ondition the 2 - wire bus will be monitored by da9053 for a valid slave address when ever the interface is enabled. it responds immediately when it receives its own slave address. th is acknowledge is done by pulling the so line low during the following clock cycle (white blocks marked with an a in figure 12 to figure 16 ). sk / slk so / data
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 66 of 183 ? 2016 dialog semiconductor the protocol for a register write from master to slave consists of a start condition, a slave addres s with read/write bit and the 8 - bit register address followed by 8 bits of data terminated by a stop condition (all bytes responded by da9053 with acknowledge): figure 35 : 2 - w ire b yte w rite (so/data l ine) when the host reads data from a register it first has to write access da9053 with the target register address and then read access da9053 with a repeated start or alternatively a second start c ondition. after receiving the data the host sends not acknowledge and terminates the transmission with a stop condition: figure 36 : examples of 2 - w ire b yte r ead (so/data line) consecutive (page) read out mode is initiated from th e master by sending an acknowledge instead of not acknowledge after receipt of the data word. the 2 - wire control block then increments the address pointer to the next 2 - wire address and sends the data to the master. this enables an unlimited read of data b ytes until the master sends a not acknowledge directly after the receipt of data, followed by a subsequent stop condition. if a non - existent 2 - wire address is read out then the da9053 will return code zero: figure 37 : examples of 2 - w ire p age r ead (so/data line) note the slave address after the repeated start condition must be the same as the previous slave address. consecutive (page) write mode is supported if the m aster sends several data bytes following a slave reg ister address. the 2 - wire control block then increments the address pointer to the next 2 - wire address, stores the received data and sends an acknowledge until the master sends the stop condition. slaveadr w regadr a data a p s = start condition a = acknowledge ( low) p = stop condition w = write (low) master to slave slave to master 7 - bits 1 - bit 8 - bits 8 - bits a s s slaveadr w a regadr a slaveadr a s = start condition a = acknowledge ( low) sr = repeated start condition a * = not acknowledge p = stop condition w = write (low) r = read (high) master to slave 7 - bits 1 - bit 8 - bits 7 - bits data a * sr r 1 - bit 8 - bits slaveadr a 7 - bits data p s r 1 - bit 8 - bits p a * slave to master s slaveadr w a regadr p 7 - bits 1 - bit 8 - bits a s slaveadr w a regadr a slaveadr a s = start condition a = acknowledge (low) sr = repeat start condition a * = not acknowledge p = stop condition w = write (low) r = read (high) master to slave slave to master 7 - bits 1 bit 8 - bits 7 - bits data a sr r 1 - bit 8 - bits s sl aveadr w a regadr a slaveadr a 7 - bits 1 - bit 8 - bits 7 - bits data p s r 1 - bit 8 - bits p a a * p data data a a * data 8 - bits 8 - bits 8 - bits
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 67 of 183 ? 2016 dialog semiconductor figure 38 : 2 - w ire p age w rite (so /data line) an alternate write mode receiving alternated register address and data can be configured to support host repeated write operations that access several but non - consecutive registers. data will be stored at the previously received register addres s: figure 39 : 2 - w ire r epeated w rite (so/data line) if a new start or stop condition occurs within a message, the bus will return to idle - mode. 10.4 alternat ive h igh s peed 2 - w ire i nterface the high speed 2 - wire (hs - 2 - wire ) interface is the alternat iv e serial control bus, which consists of a data (data line) and a clk (clock line) . it can be used as an independent control interface for data transactions between da9053 and a second host processor. the da9053 high speed 2 - wire interface ha s a configurable 8 - bit slave write address (default: 0x92) and a configurable slave read address (default: 0x93). the interface is enabled if data was selected via configuration gpio14_pin. the bus lines have to be pulled high by external pull - up resistor s (2 k ? to 20 k ? range). gpio15_ type defines the supply rail of the interface (used for input logic levels and the internal pull - up resistors). the controls gpio15_pin and gpio15_ mode are disabled when the interface is enabled via gpio14_pin. whenever the interface receives a read or write command that includes a matching slave address it is able to trigger the assertion of a nirq including an optional wake - up event (enabled via gpio14_ mode). note if the nirq assertion from interface access is enabled (e _gpi4) it may by masked as long as the hs - 2 - wire is in use (this nirq cannot be cleared via the hs - 2_ wire interface because every interface access will trigger a re - assertion) . beside the interface base address and the optional wake - up , the characteristic s of the hs - 2 - wire interface are identical to the power manager 2 - wire interface ( see 10.3.1 details of the 2 - w ire c ontrol b us p rotocol ). s s laveadr w a regadr a data a s = start condition a = acknowledge (low) sr = repeat start condition a * = not acknowledge p = stop condition w = write (low) r = read (high) master to slave slave to master 7 - bits 1 bit 8 - bits 8 - bits data a 1 - bit 8 - bits a p data . a 8 - bits repeated writes s s laveadr w a regadr a data a s = start condition a = acknowledge (low) sr = repeat start condition a * = not acknowledge p = stop condition w = write (low) r = read (high) master to slave slave to master 7 - bits 1 bit 8 - bits 8 - bits regadr a 1 - bit 8 - bits a p data . a 8 - bits repeated writes
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 68 of 183 ? 2016 dialog semiconductor 11 o perating m odes 11.1 active m ode da9053 enters active m ode after the host processor has performed at least one initial alive watchdog write (or alternatively an initial assertion of the keep_act pin) within the target time window (this watchdog condition can be disabled). a running application is typically in active m ode . i n this mode the pmic core functions ( for example ldocore, bcd counter, internal oscillator) as well as a supplies for features like battery charger and gp - adc are enabled. in active m ode the host processor can take over the control of the automatic battery charging block if necessary and is able to respond to any faults that have been detected. status information can be read from the host processor via the power manager bus and the da9053 can flag interrupt requests to the host via a dedicated interrupt port (nirq). temperature and voltages inside and outside the da9053 can be monitored and any f ault conditions flagged to the host processor. 11.2 power - down m ode da9053 is in power - down m ode whenever the power domain system is disabled (even partially). this can be achieved when progressing from reset m ode or by returning from active m ode. a return from active m ode is initiated by low - power mode instructions from the host or happens as an interim state during an application shutdown to reset m ode. during power - dow n m ode the ldocore, the band - gap, the nonkey and the bcd c ounter are activ e. in addition gpio - ports, the gp - adc, battery charger and the control interfaces keep on running if not disabled. also dedicated power supplies can be enabled in power - down m ode if power down voltages ha ve been pre - configured during active m ode. the inter nal oscillator (2 mhz) will only run on demand ( for example for a running gp - adc or bucks that are enabled and are not forced to pfm mode). the application supervision by watchdog timer is discontinued in power - down m ode. t he digital control logic of disab led features of da9053 (regulators, bucks, chargers, boosts, gp - adc, and others ) will be disconnected from the clock tree via clock gating , so that the device offer s an optimized dissipation power in power - down m ode. following the next wake - up event all su pplies are re - configured with their default voltage values from otp and the sequencer timers are set to their default otp values. if the power - down m ode was caused by releasing sys_en the sequencer pointer is located at position 0 this allows default en abl ing /disabling of supplies (beside ldocore). 11.3 reset m ode da9053 is in reset m ode whenever a complete application reset is required. the reset m ode happens after cold start when progressing from no - power m ode or can be forced by the user via a pressed reset switch that is connected to port nshutdown, a long press of nonkey (if its reset feature was enabled) or a long parallel assertion of gpio14 and gpio15 (if this reset feature was enabled), from the host processor by asserting port nshutdown or via an error detection from da9053. da9053 error conditions that force a reset m ode: a w atchdog write from the host outside of the watchdog time window (if watchdog was enabled) an under - voltage detected at vddout (v ddout < v dd_fault_lower ) an internal die over - temper ature detected an over voltage or over current at the boost
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 69 of 183 ? 2016 dialog semiconductor in order to allow the host to determine the reason for the reset a faultlog register records the cause. when returning from power - down m ode the reset m ode will be achieved after powering down do main system completely and continue towards a state with absolute minimum current consumption, with the only active circuits being ldocore, the bcd counter, the band gap and the vdd_ref , vbus, dcin, acc_id_det and vddout comparators. beside supplies (contr olled by the power sequencer) and the backup battery charger , other blocks on da9053 (for example the backlight boost ) are automatically disabled to avoid draining the battery. during da9053 reset m ode the host processor can be held in a reset state via po rt nreset that is always asserted to low when da9053 progresses from reset mode ( for example after cold start from no - power m ode) and can be asserted (depending on configuration of sequencer step 0) when the sequencer has finished powering down domain syst em (even partially) . some reset conditions like the shutdown via register bit, watchdog error, or over - temperature , will automatically expire. other conditions like asserting the port nshutdown need to be released to enable a progress ion from reset to pow er - down m ode. if the reset was initiated by the user a 500 ms time out will be inserted before trying to power up again. when the reset condition has disappeared da9053 requires either a connected good main battery (v ddout > v dd_fault_upper ) or a detected supply (vbus/dcin > vch_thr) that is able to provide enough power to vddout (v ddout > v ddout_min ) to start up to power - down m ode. 11.4 no - power m ode da9053 will enter the no - power m ode when the internal supply rail v dd_ref drops below v por_lower ( for example du ring continued discharge of main and backup battery). as long as v dd_ref is now lower than v por_upper the core supply ldocore, the 32k oscillator and the bcd counter are switched off, an internal power - on - reset (npor) is asserted and only the vdd_ref compa rator is active and checks for a condition that allows da9053 to turn on again. when da9053 detects either a good main battery or a connected supply charger which r a ises v dd_ref > v por_upper it will reset the bcd counter and progress to reset m ode. 11.5 power c ommander m ode this is a special mode for evaluation and configuration. in p ower c ommander m ode da9053 is configured to load the control register default values from the hs 2 - wire interface instead of from the otp cells so that unprogrammed da9053 samples w ill power up and allow a pc running p ower c ommander software to load all the configuration registers. power c ommander m ode is enabled by connecting tp to vddcore. in reset m ode da9053 will do an initial otp read to setup the trim values. however, if the otp values loaded into these registers are not as required they can be updated during the subsequent p ower c ommander programming sequences. note in p ower c ommander m ode gpi14/15 will be configured for hs - 2 - wire interface operation (with vddcore as the supply) and gpo13 will be configured as an output for nvdd_fault. any register writes or otp loads which can change this configuration are ignore d until da9053 has exited from p ower c ommander m ode. after the initi al otp read has completed da9053 informs the system that it is waiting for a programming sequence by driving nvdd_fault low. the software running on the pc monitors nvdd_fault and responds by downloading the values into the configuration registers within d a9053. nvdd_fault is automatically released after the release register is loaded. there are two programming sequences performed in p ower c ommander m ode. the first takes place between reset and power - down mode and the second takes place between power - down a nd system mode . two release registers are used support these two programming sequences:
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 70 of 183 ? 2016 dialog semiconductor a write to register r106 will end the first programming sequence a write to register r61 will end the second programming sequence during these programming sequences an y registers can be written to in any order, but the sequence will terminate after the appropriate release register has been written to. note to correctly configure da9053 registers, r10 to r105 should be programmed during the first sequence and fault log register (r9) bit vdd_fault has to be cleared by writing a 1. registers r14 and r43 to r61 should be programmed during the second sequence. the host can determine whether da9053 is in the first or second programming sequence by reading the fault log reg ister. if a read of the fault log register bit vdd_fault returns a zero, then the da9053 is in the second programming sequence otherwise it is in the first. after the first programming sequence has been completed da9053 will be in power - down m ode. progression from this mode is determined by the values programmed for sys_en and auto_boot. if da9053 has been directed to progress from power - down m ode then it will drive pin nvdd_fault low for a second time to request that the sw performs the second programming sequence. once the second programming sequence has completed the progress of the power - up sequence will be controlled by the values loaded during the programming sequence. the programmed configuration can be identified by reading the fuse regi ster config_id. note during p ower c ommander m ode the fault detection status bit vdd_fault and the level at the related pin nvdd - fault do not match and does not indicate a low voltage level at vddout. an enabled shutdown from the 5 s assertion of gp io14/15 will be ignored during p ower c ommander m ode.
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 71 of 183 ? 2016 dialog semiconductor 11.6 start - u p from no - power m ode 11.6.1 power - on - reset (npor) to guarantee the correct start - up of da9053 an internal power - on - reset npor (active low) is generated for the initial connection of either a supply or a good battery following a phase of not being supplied with sufficient power. to allow da9053 to start up , even if the main battery is completely discharged , an internal vdd_ref rail is used to supply the charger blocks, comparators and the control logic. if no charger is present vdd_ref is switched to either the main battery or the backup battery, whichever provides the higher voltage level. if the backup battery was connected to the application before main power, da9053 remains off and draws no current. this al lows the application to wait for its initial activation without discharging the backup battery. while v ddcore < v por_upper the internal npor is asserted and da9053 will not switch on (no - power m ode). when v ddcore rises above v por_upper the npor is negated , ldocore is switched on, the bcd counter and fault_log register are reset and da9053 progresses to reset m ode. when an external charger is detected (rising edge on dcin_det or vbus_det) having no , or only a deep discharged , main battery connected to da90 53 the internal charger, oscillator and band - gap are enabled and the whole otp trim block is read and stored to the register bank. if the supply voltage is below the charger detection threshold (vch_thr) after a debouncing period of tdelay (10 ms, to allow for de - bouncing of the input signal and the band - gap reference to settle) the device returns to reset mode. if the external charger is still present and the chg_att comparator flags a minimum of 100 mv head room from charger input vcenter to vddout da905 3 starts up the charger buck to supply vddout at the default current limit (loaded from otp) and starts supplying power to vddout, which enables an application start - up also with a flat battery. when v ddout rises above v ddout_min da9053 enters the power - do wn m ode. if this does not happen within 128 ms it will return to reset mode. from power - down m ode da9053 will continue with powering up supplies if the power domain system was asserted via input port (or set via otp settings) and auto_boot was enabled (or a valid wake - event has happened). the simplified flow diagram , ( figure 40 ) , shows the start - up events and an example of a typical initial sequence. if da9053 causes a reset from an under voltage detected within 10 s after releasing nreset (the start - up initiating s upply is not strong enough to supply the application) da9053 will assert vdd_start inside the faultlog register and temporally disable auto_boot for the consecutive start - up (enabling only the battery charger and start waiting for a valid wake - up event). o nly events generated from user inputs (gpis or nonkey) trigger a wake - up during this emergency charging , however a flashing led connected to gpio 11 or 11 can be automatically enabled via control blink_frq. auto_boot is set back to its default value when t he battery voltage v bat > vchg_bat - vchg_drop. a similar start - up to power - down m ode will be performed when a pre - charged battery was inserted (v ddout >v dd_fault_upper ) following a state where da9053 has not been provided with any supply voltage as shown in figure 40 .
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 72 of 183 ? 2016 dialog semiconductor figure 40 : start - u p from no - power to power - down m ode 11.7 application w ake - u p a valid w ake - up event ( for example nonkey , sys_en, rtc - alarm or a trigger from gpios) initiates an application power up from power - down mode . the w ake - up from gpios (or selected alternat ive features, that use a shared gpi event) has to be enabled via gpix_mode and can be masked in addition with t he related nirq mask. after a w ake - up condition is detected the otp trim block for all supplies and the sequencer timer is read (r14 and r43 - r61) . t he values (re - )configure the supplies and the sequencer timer. if the power - down mode was reached by progres sing from reset mode the power sequencer can also be started without waiting for a w ake - up event if auto_boot was asserted. da9053 will assert the ext_wakeup signal toward the host processor and if the power domains are not pre - enabled by otp the host pro cessor has to control the further application start - up ( for example via the power domain enable lines). alternatively da9053 continues stand - alone powering up the otp enabled domains via the power domain sequencer. by that a start - up from reset mode powers up the application automatically only if sys_en is asserted from the host processor or was default set from otp. continuation into active mode requires an assertion of pwr_en (from the host via port pwr_en, register write or enabled from otp). after start ing the watchdog timer the host processor has the configured time window to assert the watchdog timer via the power manager bus (if watchdog is enabled). if this does not happen the state - machine will terminate the active mode at the end of the time window and return to the reset mode. 11.8 system m onitor ( w atchdog) after powering up domain power , da9053 can initiate an initial w atchdog monitor function (if this feature is enabled via control twdscale). if the watchdog is enabled the host processor has to write logic 1 within a configured time ( twdmax ) to bit watchdog in da9053 register r17 to indicate that it is alive after pwr_up was asserted. if the host does not write 1 to the watchdog bit within the twdmax time da9053 will assert twd_error in the fault _log register and power down to reset mode . after this first write to the watchdog bit the host must write again to the watchdog bit within a configured time window or da9053 will assert twd_error in the fault_log register and power down to reset mode . the watchdog error condition is cleared when entering the reset mode . the time window has a minimum time twdmin fixed at 256 ms and a maximum time twdmax of nominally 2.048 s. the twdmax value can be extended by multiplying the nominal twdmax by the r e s e t r e a d o t p r e a d o t p v b u s _ d e t r i s i n g v d c i n _ d e t r i s i n g t d e l a y 1 0 m s t d e l a y 1 0 m s t d e l a y 1 0 m s c h a r g e r s u p p l i e s v d d o u t t d e l a y 1 0 m s v b u s / d c i n > v c h _ t h r v d d o u t < v d d _ f a u l t _ l o w e r v d d o u t > v d d _ f a u l t _ u p p e r v d d o u t > v d d o u t _ m i n v d d o u t > v d d _ f a u l t _ u p p e r n o - p o w e r v d d c o r e > v p o r _ u p p e r v d d c o r e < v p o r _ l o w e r p o w e r - d o w n v d d o u t < v d d o u t _ m i n 1 2 8 m s t i m e o u t
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 73 of 183 ? 2016 dialog semiconductor register bits twdscale. twdscale is used to extend the twdmax time by x1, x2, x4, x8, x16, x32 or x64. changing the maximum value of the time window (twdmax) or the state of keepact_en bit requires twdscale to be zero (watchdog is disabled) for a minimum of 100 s . this requires the host to first switch off the watchdog for at least 150 s before configuring it with a new timing window scale value (twdscale). the watchdog bit can also be asserted from the host via hardware by asserting keep_act. this mode is select ed via control keepact_en, which disables the control of the watchdog bit via the host control interface. the ( in time ) assertion of nonkey will then also enable da9053 to transfer into active mode. once in the active state da9053 will continue to monitor the system unless it is disabled via setting twdscale to zero. if the watchdog register bit is set to a 1 within the time window the w atchdog monitor resets the timer, sets the watchdog bit back to zero (bit is always read as zero) and waits for the next w atchdog signal. 11.9 wake - u p e vents table 45 : wake - u p e vents signal / condition wake - up user event system event irq charger attach: e_dcin_det x x x charger attach: e_vbus_det x x x charger removal: e_dcin_rem x x x charger removal: e_vbus_rem x x x vddout low pre - warning: e_vdd_low x x x rtc alarm: e_alarm x x x sequencing finished: e_seq_rdy x x voltage comparator: e_comp_1v2 x x x pressed on - key: e_nonkey x x x accessory and usb id detect (id_float falling edge) x x x accessory and usb id detect (id_float rising edge) x x end of battery charging: e_chg_end x x x battery temperature: e_tbat x x manual adc result ready: e_adc_eom x x pen down detection from tsi: e_pen_down x x x measurement ready from tsi: e_tsi_ready x x gpios: e_gpix x x x adc 4, 5, 6 threshold: via gpi0, 1, 2 x x x sys_en, pwr_en, pwr1_en (passive to active transition): via gpio8, 9, 10 x x x hs - 2 - wire interface: via gpio14 x x x
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 74 of 183 ? 2016 dialog semiconductor power supply s equencer the start - up of da9053 supplies is performed with a sequencer that contains a programmable step timer, a variable id array of time slot pointers and four predefined pointers (system_end, power_end, max_ count and part_down). the sequencer is able to control up to 22 ids (4 buck converter, 2 rail switches vperi_sw_en / vmem_sw_en, 10 ldos, 4 feedback pin level controls, a wait id (gpi10) and a power - down register), which can be grouped in three power domai ns. the power domains have configurable size and their borders are described by the location pointers system_end, power_end and max_count. the lowest level power domain system starts at step 1 and ends at the step that is described by the location pointer system_end. the second level domain power starts at the successive step and ends at power_end. the third level domain power1 starts at the consecutive step and ends at max_count. the values of pointer system_end, power_end and max_count are predefined in otp registers. and should be configured to be system_end < power_end < max_count. the domain system by can be understood as a basic set of s upplies that are mandatory to keep the application at least inside a standby/hibernate mode. if enabled via control otpread_en all supplies of da9053 and the sequencer timer (registers r14 and r43 - r61) are configured with the default value from otp before powering up the domain system. this will cause a reconfiguration of all supplies that ha ve been powered down with a preset voltage level. the second level domain power includes supplies that are required in addition to get the application alive and set d a9053 in to active mode. power1 can be understood as a sub domain of power that can be used for additional hardware/software initiated control of supply blocks during active mode ( for example for a sub - application like wlan or gsm baseband). supplies in do main power and power1 can be voltage preconfigured and after that sequentially changed during powering down, but will not be reset to their default values from otp unless there is a power - up from domain system. note running applications should be configur ed to active mode (domain power is up) and pointer power_end has to be at least one time slot higher than system_end . all buck converter and 10 ldos of da9053 have received a unique sequencer id. the power - up sequence is then defined by an otp register ba nk that contains a series of supplies (and other features), which are pointing towards a sequencer time slot. several supplies can point in to the same time slot and by that will be enabled by the sequencer in parallel. time slots that have no ids pointing towards it are dummy steps that do nothing but insert a configurable time delay (marked as d in figure 42 ). supplies that are not pointing towards a sequencer time slot (with a step number greater than zero and less than max_count) will not be enabled by the power sequencer and have to be control led individually by the host (via the power manager bus). figure 41 : content of otp power sequencer register c ell o t p s t e p 0 l s b i f a s s e r t e d a l l s u p p l i e s a r e s e t t o d e f a u l t m o d e w h e n p r o c e s s i n g s t e p 0 ( b e s i d e l d o c o r e ) 0 0 0 0 o t p s t e p 1 - 1 5 4 b i t 0 0 0 0 0 : d u m m y ( d o n o t h i n g ) 1 C 1 5 : e n a b l e s u p p l y d e s c r i b e d b y i d 0 : n o a s s e r t i o n o f n r e s e t d u r i n g p o w e r - d o w n m o d e 1 : s t a r t r e s e t t i m e r f r o m s e l e c t e d e v e n t d u r i n g p o w e r i n g u p n o t u s e d 0 : a s s e r t s y s _ u p d e r i v e d f r o m d o m a i n s u p p l i e s p r e s e t t i n g 1 : d e - a s s e r t s y s _ u p b e f o r e p o w e r i n g d o w n d o m a i n s y s t e m m s b c o n f i g u r e s e q u e n c e r
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 75 of 183 ? 2016 dialog semiconductor during powering up the sequencer will start at step 0 where the sequencer behaviour is configured. if def_supply is asserted this includes an optional enabling of supplies (depending on the otp default settings of the supplies). if sys_en was asserted via port or otp , the sequencer will assert the ready signal (if selected for the feedback pin) and continue with step 1 ( th is enables all supplies (features) from the otp register bank that are pointing towards step 1 ) the sequencer will progress until it has reached the position of pointer system_end. once all supplies of the first power domain system are enabled , da9053 will assert the output signal sys_up, release the ready signal and assert the e_seq_rdy interrupt. note it is recommended that supplies having an asserted enable bit in the otp are not controlled via ids of the power sequencer if def_supply is asserted (ids of these supplies should point into time slot 0). table 46 : powe r sequencer controlled a ctions action sequencer time s lot step 0: configure power sequencer id_0 ldo1_en ldo1_step ldo2_en ldo2_step ldo3_en ldo3_step ldo4_en ldo4_step ldo5_en ldo5_step ldo6_en ldo6_step ldo7_en ldo7_step ldo8_en ldo8_step ldo9_en ldo9_step ldo10_en ldo10_step pd_dis pd_dis_step vperi_sw_en vperi_sw_step vmem_sw_en vmem_sw_step bcore_en buckcore_step bpro_en buckpro_step bmem_en buckmem_step bperi_en buckperi_step assert/release gp_fb2 gp_rise1_step assert/release gp_fb2 gp_rise2_step release/assert gp_fb2 gp_fall1_step release/assert gp_fb2 gp_fall2_step wait for active state at gpi 10 wait_step note ids not controlled by the sequencer (or enabled via def_supply in step 0) should point into step 0 .
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 76 of 183 ? 2016 dialog semiconductor figure 42 : allocation of s upplies (ids) to the s equencer t ime s lots to continue , the sequencer checks for pwr_en to be asserted (via pwr _en port, register write or otp). when this is available the feedback signal ready will be asserted and supplies of domain power will be enabled sequentially. the sequencer stops at step power_end, releases the ready signal, asserts pwr_up, assert the e_se q_rdy interrupt, enables the initial watchdog timer and waits for an alive feedback from the host processor which starts the active mode of da9053 and releases an asserted ext_wakeup signal. a third power domain power1 can be enabled from pwr1_en (assert ed via pwr1_en port, register write or otp). it will enable all consecutive supplies until step max_count has been reached, assert pwr1_up and assert the e_seq_rdy interrupt. the ready signal will be asserted as long as ids are processed (if enabled). the domain power1 offers no dedicated status indicator, but the end of its power - up sequence can be selected to start the reset timer. the delay between the steps of a sequence is controlled via a 4 - bit otp programmable timer unit seq_time with a default delay of 1285 s per step (min. 32 s and max. 816 ms). the delay time between individual supplies can be extended by leaving consecutive steps with no ids pointing to it (dummy supply), which provides an independent delay configured via control seq_dummy. the delay timers are configured with their default values from otp (r43) every time before powering up inside domain system. note during entering and leaving a power domain a 32 s delay will always be inserted . when da9053 is powering down the sequencer will disable the supplies in reverse order and timing. supplies that are configured with a preset value (ldox_conf or buckxxx_conf bit is set) wil l not be disabled but configured with its preset voltage when the related time slot/id is processed. if a domain contains at least one supply with an assigned preset, the power domain status indicator (pwr1_up, pwr_up and sys_up) will not be released. othe rwise the indicator will be released before the first supply of a power domain will be disabled (a de - assertion of sys_up can be forced via step 0 configuration). if powering down was initiated from releasing pwr_en1 the sequencer will stop to modify suppl ies when the domain pointer power_end was reached. if pwr_en was disabled the domain power1 will be powered down followed by power until the sequencer reaches pointer system_end. if sys_en was disabled the sequencer will process all ids lower than the actu al pointer posi tion down to step 0. if the low - power mode was initiated by asserting the control register deep_sleep the sequencer will first power down power1 and power continue l d o 1 l d o 2 l d o 3 l d o 4 l d o 5 l d o 6 l d o 7 l d o 8 p d _ d i s v c o r e _ s w v m e m _ s w b u c k c o r e b u c k p r o b u c k m e m b u c k p e r i s e q u e n c e r i d ( o t p c e l l ) t i m e s l o t 0 1 2 3 d 5 d 7 d d 1 0 d d 1 3 1 4 1 5 4 p o w e r _ e n d s y s t e m _ e n d o s c p r o g r a m m a b l e 4 b i t o t p s t a r t / s t o p s y s _ e n o t p e n a b l e m a x _ c o u n t s e q u e n c e r p a r t _ d o w n s y s t e m p o w e r p o w e r 1 p o w e r d o m a i n p a r t _ d o w n l d o 9 l d o 1 0 g p _ r a i s e 1 g p _ r a i s e 2 g p _ f a l l 1 g p _ f a l l 2 w a i t
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 77 of 183 ? 2016 dialog semiconductor with system and stop when pointer part_down has been reached (part_down has t o point into domain system). if sys_en was disabled the sequencer will process all ids lower than the actual pointer position down to step 0 (ignoring the part_down pointer). the sequencer asserts the e_seq_rdy interrupt whenever reaching the target pointe r position. during processing step 0 all supplies (beside ldocore) can be set to their otp default state (if bit def_supply of step 0 is asserted), but the voltage levels are unchanged. because of adding rush currents on the battery it is not recommended t o default enable more than a single supply at step 0. asserting control register bit shutdown will first power down to step 0 and then forces da9053 to reset m ode. da9053 features, for example, the 32k output buffer or an auto adc measurement can be disabl ed temporarily in power - down mode via register pd_dis. the timing for processing pd_dis can be defined by the placement of pd_dis inside the sequence. the temporally disable will be discontinued features asserted in pd_dis are enabled when pd_dis is proces sed during a the next power - up sequence. if the ready signal is enabled, it will be asserted during processing the ids for powering down. note any reconfiguration of supplies from the host in active mode will not affect the domain status indicators (sys_up, and pwr_up) and by that has to be performed carefully. the sequencer will later only check for supplies with an assigned preset configuration bit; others will keep their actual voltage level unchanged during power mode transitions. powering up fro m domain sys_en will configure all supplies and the sequencer timer with the default values from otp (r14 and r43 - r61). during sequencing (indicated from da9053 via signal ready or the e_seq_rdy interrupt) the host is not allowed to send additional power m ode transition requests (via power manger interface or power domain enable lines). a conditional mode transition can be achieved using id wait_step. if pointing into the sequence the progress of an initiated mode transition can be synchronized , for exampl e with the state of a host, that is indicated via a signal connected to gpi10. via gpio10_ mode a security time - out of 500 ms can be selected, that will trigger a power down to reset mode (including the assertion of wait_shut inside register fault_log) if e_gpi10 was not asserted until then. note in the case of a shutdown sequence towards reset mode (or power - down from fault condition) any waiting from id wait_step will be skipped. when powering up from no_power mode id wait_step can alternatively be used as a configurable delay to allow the 32k oscillator to stabilize before the ttl signal is provided at the 32k output pin (see register wait_cont). the configuration at sequencer step 0 (nres_mode) enables the assertion of nreset at the end of a power down sequence and starting the reset timer during the consecutive powering up. this is also true for partial power - down mode , when the sequencer powers down to pointer position part_down. the reset timer will start to run from the selected event reset_event an d release the nreset port after the reset timer has expired (see also description for powering up from no - power/reset mode ) . note by connecting tp to vddcore da9053 can be configured to load control register default values from the hs 2 - wire interface ins tead of from the otp cells. during start - up the power sequencer will then assert pin nvdd_fault (set to zero) and wait until an external device has loaded default values into the control registers r10 to r106 after reset mode (if vdd_fault is asserted), r1 4 and r43 to r61 when leaving power - down mode (if vdd_fault is not asserted) , via hs 2 - wire interface. the host has to clear the fault_log register after loading r10 to r106. when the last register has been loaded nvdd_fault will be released and the start - up sequence is continued. during this mode the settings of gpi14 and 15 will be ignored (pins are assigned as 2 - wire interface supplied from vddcore).
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 78 of 183 ? 2016 dialog semiconductor system m onitor (watchdog) after powering up domain power da9053 can initiate an initial watchdog monitor function (if this feature is enabled via control twdscale). if the watchdog function is enabled the host processor has to write logic 1 within a configured twdmax time to bit watchdog in da9053 register r17 to indicate that it is alive after pwr_up was asserted. if the host does not write 1 to the watchdog bit within the twdmax time da9053 will assert twd_error in the fault_log register and power down to reset mode . after t his first write to the watchdog bit the host must write again to the watchdog bit within a configured time window or da9053 will assert twd_error in the fault_log register and power down to reset mode . the watchdog error condition is cleared when entering the reset mode . the time window has a minimum time twdmin fixed at 256 ms and a maximum time twdmax of nominally 2.048 s. the twdmax value can be extended by multiplying the nominal twdmax by the register bits twdscale. twdscale is used to extend the twdma x time by x1, x2, x4, x8, x16, x32 or x64. changing the maximum value of the time window or the state of the keepact_en bit requires twdscale to be zero (watchdog is disabled) for a minimum of 100 s. this requires the host to first switch off the watchdo g for at least 150 s before configuring it with a new timing window scale value (twdscale). the watchdog bit can also be asserted from the host via hardware by asserting keep_act. this mode is selected via control keepact_en, which disables the control of the watchdog bit via the host control interface. the in time assertion of nonkey will then also enable da9053 to transfer into active mode. once in the active state da9053 will continue to monitor the system unless it is disabled via setting twdscale to zero. if the watchdog register bit is set to a 1 within the time window the watchdog monitor resets the timer, sets the watchdog bit back to zero (bit is always read as zero) and waits for the next watchdog signal.
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 79 of 183 ? 2016 dialog semiconductor 12 register page c ontrol table 47 : register p age 0 register a d dress bit type label description r00 page_con_p0 6:0 r reserved 7 rw reg_page 0: selects register r1 to r127 1: selects register r129 to r255 12.1 power ma nager c ontrol and m onitoring the status register reports the current value of the various signals at the time that it is read out. note all the status bits have the same polarity as their corresponding signals . register bits in blue are loaded from otp . register a d d ress bit type label description r01 status_a 0 r nonkey current nonkey state 1 r id_float current id_float detector value 2 r id_gnd current id_gnd detector value 3 r dcin_det 0: dcin voltage not detected (@ dcin pin) 1: dcin voltage detected 4 r vbus_det 0: vbus voltage not detected (@ vbus pin) 1: vbus voltage detected 5 r dcin_sel 0: no valid charger at dcin (over voltage) 1: dcin charger selected 6 r vbus_sel 0: no valid charger at vbus (over voltage) or dcin charger received priority 1: vbus charger selected 7 r vdat_det 0: usb host/hub detected (100 ma) 1: dedicated or host/hub charger detected register a d dress bit type label description r02 status_b 0 r chg_att 0: no charger attached (drop from vcenter to vddout < 100 mv) 1: charger attached (drop from vcenter to vddout > 100 mv) 1 r chg_pre charging mode when chg_end is not asserted 0: charger is in fast cc/cv mode 1: charger is in pre - charge mode 2 r chg_lim 0: charging as configured
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 80 of 183 ? 2016 dialog semiconductor register a d dress bit type label description 1: charge current in constant current mode reduced to less than ichg_thd 3 r chg_end 0: battery charging 1: battery charging completed cleared automatically when starting charging/re - charging 4 r chg_to 0: battery charging timer ok or disabled 1: battery charging timeout caused charging finished cleared automatically when starting charging/re - charging and when loading tctr 5 r gp_fb2 status of gp_fp2 pin: configured from power sequencer 6 r sequenci ng 0: sequencer is idle 1: sequencer is processing ids 7 r comp_det 0: comparator at adcin5 (1.2 v) not asserted 1: comparator asserted register a d dress bit type label description r03 status_c 0 r gpi0 gpi0 level or adcin4 threshold indicator (1 when overriding high limit) 1 r gpi1 gpi1 level or adcin5 threshold indicator (1 when overriding high limit) 2 r gpi2 gpi2 level or adcin6 threshold indicator (1 when overriding high limit) 3 r gpi3 gpi3 level 4 r gpi4 gpi4 level 5 r gpi5 gpi5 level 6 r gpi6 gpi6 level 7 r gpi7 gpi7 level register a d d ress bit type label description r04 status_d 0 r gpi8 gpi8/sys_en level 1 r gpi9 gpi9/pwr_en level 2 r gpi10 gpi10/pwr1_en level 3 r gpi11 gpi11 level 4 r gpi12 gpi12/ext_wakeup/ready level 5 r gpi13 gpi13 level
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 81 of 183 ? 2016 dialog semiconductor 6 r gpi14 gpi14 level 7 r gpi15 gpi15 level the event registers hold information about events that have occurred in da9053. events are triggered by a change in the status registers that contains the status of monitored signals. when an event bit is set in the event register the nirq signal shall be asserted (unless the nirq is to be masked by a bit in the irq mask register). the nirq is also masked during the power - up sequence and will not be released until the event registers have been cleared. the irq triggering event register will be cleared from the host by writing a byte containing a 1 at the bit to be reset (bits written containing a zero will leave the related event register bits unchanged). the event registers may be read in page/repeated mode. new events that occur during clearing will be delayed before they are passed to the event register, ensuring that the host controller does not miss them. register a d dress bit type label description r05 event_a note 1 0 r e_dcin_det dcin detection caused event 1 r e_vbus_det vbus 4.4 v detection caused event 2 r e_dcin_rem dcin removal caused event 3 r e_vbus_rem vbus removal caused event 4 r e_vdd_low vddout less than vddout_mon threshold caused event 5 r e_alarm rtc alarm caused event 6 r e_seq_rdy sequencer reached stop position caused event 7 r e_comp_1v2 1.2 v comparator caused event note 1 cleared by writing from host with bit assigned to 1 (bits containing zero during writing do not change event register bits) . register a d dress bit type label description r06 event_b note 1 0 r e_nonkey nonkey caused event 1 r e_id_float accessory detection change caused event (rising and falling edge of id_float, only falling edge during power - down mode) 2 r e_id_gnd accessory detection change caused event (rising and falling edge of id_gnd) 3 r e_chg_end battery charging complete caused event 4 r e_tbat battery over/ under temp caused event 5 r e_adc_eom adc manual conversion result ready caused event 6 r e_pen_down pen down detection caused event 7 r e_tsi_ready tsi sequence (xp, xyp, xyzp) finished caused event
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 82 of 183 ? 2016 dialog semiconductor note 1 cleared by writing from host with bit assigned to 1 (bits containing zero during writing do not change event register bits) . register a d dress bit t ype label description r07 event_c note 1 0 r e_gpi0 gpi event according to active state setting/ adcin4 high / low threshold exceeded caused event 1 r e_gpi1 gpi event according to active state setting/ adcin5 high / low threshold exceeded caused event 2 r e_gpi2 gpi event according to active state setting/ adcin6 high / low threshold exceeded caused event 3 r e_gpi3 gpi event according to active state setting 4 r e_gpi4 gpi event according to active state setting 5 r e_gpi5 gpi event according to active state setting 6 r e_gpi6 gpi event according to active state setting 7 r e_gpi7 gpi event according to active state setting note 1 cleared by writing from host with bit assigned to 1 (bits containing zero during writing do not change event register bits) . register a d d ress bit type label description r08 event_d note 1 0 r e_gpi8 gpi event according to active state setting/sys_en assertion caused event 1 r e_gpi9 gpi event according to active state setting/pwr_en assertion caused event 2 r e_gpi10 gpi event according to active state setting/pwr1_en assertion caused event 3 r e_gpi11 gpi event according to active state setting 4 r e_gpi12 gpi event according to active state setting 5 r e_gpi13 gpi event according to active state setting 6 r e_gpi14 gpi event according to active state setting/event caused from host addressing hs - 2 - wire interface 7 r e_gpi15 gpi event according to active state setting note 1 cleared by writing from host with bit assigned to 1 (bits containing zero during writing do not change event register bits) . the nirq line will be released only when all events have been cleared from the host processor by writing a 1 to each asserted event bit (to prohibit missing events it is recommended to clear event bits individually).
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 83 of 183 ? 2016 dialog semiconductor register a d d ress bit type label description r09 fault_log note 1 note 2 0 r twd_error watchdog time violated 1 r vdd_fault power down by vddout under voltage detect 2 r vdd_start power down by vddout under voltage detect within 10 s from releasing nreset 3 r temp_over junction over temperature detected 4 r reserved 5 r key_shut power down by a long press of the nonkey or gpi14 and gpi15 in parallel 6 r nsd_shut power down by assertion of port nshutdown 7 r wait_shut power down by time out of id wait_step note 1 cleared by writing from host with bit assigned to 1 (bits containing zero during writing do not change event register bits) . note 2 the fault_log register has to be cleared from the host after reading by writing 11111111 . register a d dress bit type label description r10 irq_mask_a 0 r/w m_dcin_vld mask dcin detection caused nirq 1 r/w m_vbus_vld mask vbus 4.4 v detection caused nirq 2 r/w m_dcin_rem mask dcin removal caused nirq 3 r/w m_vbus_rem mask vbus removal caused nirq 4 r/w m_vdd_low mask vddout low caused nirq 5 r/w m_alarm mask rtc alarm caused nirq 6 r/w m_seq_rdy mask sequencer reached stop position caused nirq 7 r/w m_comp_1v2 mask 1.2 v comparator caused nirq register a d dress bit type label description r11 irq_mask_b 0 r/w m_nonkey mask nonkey caused nirq 1 r/w m_id_float mask id_float accessory detection change caused nirq 2 r/w m_id_gnd mask id_gnd accessory detection change caused nirq 3 r/w m_chg_end mask battery charging complete caused nirq
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 84 of 183 ? 2016 dialog semiconductor 4 r/w m_tbat mask battery over / under temp caused nirq 5 r/w m_adc_eom mask adc manual conversion result ready caused nirq 6 r/w m_pen_down mask pen down detection caused nirq 7 r/w m_tsi_ready mask tsi sequence (xp, xyp, xyzp) finished caused nirq register a d d ress bit type label description r12 irq_mask_c 0 r/w m_gpi0 mask gpi caused/ adcin4 high / low threshold exceeded caused nirq 1 r/w m_gpi1 mask gpi caused/ adcin5 high / low threshold exceeded caused nirq, should be asserted for ldo h/w control 2 r/w m_gpi2 mask gpi caused/ adcin6 high / low threshold exceeded caused nirq, should be asserted for ldo h/w control 3 r/w m_gpi3 mask gpi caused nirq 4 r/w m_gpi4 mask gpi caused nirq 5 r/w m_gpi5 mask gpi caused nirq 6 r/w m_gpi6 mask gpi caused nirq 7 r/w m_gpi7 mask gpi caused nirq register a d dress bit type label description r13 irq_mask_d 0 r/w m_gpi8 mask gpi/sys_en caused nirq 1 r/w m_gpi9 mask gpi/pwr_en caused nirq 2 r/w m_gpi10 mask gpi/pwr1_en caused nirq 3 r/w m_gpi11 mask gpi caused nirq 4 r/w m_gpi12 mask gpi caused nirq, should be asserted for ldo h/w control 5 r/w m_gpi13 mask gpi caused nirq 6 r/w m_gpi14 mask gpi/hs - 2 - wire caused nirq 7 r/w m_gpi15 mask gpi caused nirq register a d d ress bit t ype label description r14 control_a 0 r/w sys_en note 1 target status of power domain system: state of gpi8 (otp default ignored) or configuration from otp/pm interface (depended on setting at
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 85 of 183 ? 2016 dialog semiconductor gpio_8_pin) 1 r/w pwr_en note 2 target status of power domain power: state of gpi9 (otp default ignored) or configuration from otp/pm interface (depended on setting at gpio_9_pin) 2 r/w pwr1_en n ote 3 target status of power domain power1: state of gpi10 (otp default ignored) or configuration from otp/pm interface (depended on setting at gpi o_10_pin) 3 r/w pm_if_v 0: power manager if (4 - wire /2 - wire ) supplied from vdd_io1 1: power manager if (4 - wire /2 - wire ) supplied from vdd_io2 4 r/w pm_i_v nonkey, nshutdown, sys_en, pwr_en, pwr1_en are supplied from: 0: vddcore 1: vdd_io2 5 r/w pm_o_v sys_up, pwr_up, gp_fb2, out_32k, nreset, nirq are supplied from: 0: vdd_io1 1: vdd_io2 6 r/w pm_o_ type nreset, nirq output are: 0: push - pull 1: open drain 7 r/w gpi_v gpis (not configured as pm control inputs) are supplied from: 0: vddcore 1: vdd_io2 note 1 sys_en hardware control can be configured as high or low active via gpio_8_ type . note 2 pwr_en hardware control can be configured as high or low active via gpio_9_ type . note 3 pwr1_en hardware control can be configured as high or low active via gpio_10_ type . register a d dress bit type label description r15 control_b 0 r/w reserved 1 r/w act_diode battery provides power 0: through internal active diode path (mandatory, if no external fet connected!) 1: through internal active diode and external power fet 2 r/w auto_boot 0: start - up of power sequencer after progressing from reset mode requires a valid wake - up event 1: pmic automatically starts power sequencer after progressing from reset mode 3 r/w otpread_en 0: partial otp read after power - down mode disabled 1: power supplies are configured with otp values when leaving power - down mode
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 86 of 18 3 ? 2016 dialog semiconductor register a d dress bit type label description 4 r/w bbat_en 0: disables supply from backup battery 1: automatic switch of vdd_ref to backup battery enabled 5 r/w write_mode 2 - wire multiple write mode (setting used for both 2 - wire interfaces) 0: page write mode 1: repeated write mode 6 r/w deep_sleep if set to 1 da9053 goes to deep sleep mode (sequencer stops at pointer part_down). the bit is cleared back to 0 automatically before powering up from power - down mode 7 r/w shutdown if set to 1 the sequencer powers down to reset mode the bit is cleared back to 0 automatically before leaving the reset mode register a d dress bit type label description r16 control_c 0 r/w pm_fb1_pin 0: feedback pin indicates ext_wakeup events (active high) 1: feedback pin is used as ready indicator, signalling ongoing power mode transitions (power sequencer and dvc) (active low) 1 r/w pm_fb2_pin 0: feedback pin indicates the status of dom ain power 1 (active high pwr 1 _up) 1: feedback pin is used as a configurable gp_fb indicator, that is asserted from the power sequencer 4:2 r/w debouncing gpi, nonkey and nshutdown debounce time 000: no debounce time 001: 10.24 ms 010: 20.48 ms 011: 40.96 ms 100: 102.4 0 ms 101: 1024 ms 110: 2048 ms 111: 5120 ms 6:5 r/w blink_frq gpo10/gpo11 flashing frequency 00: no blinking 01: every second 10: every two second 11: every two seconds enabled during pre - charge mode and emergency charging 7 r/w blink_dur gpo10/gpo11 flashing on - time 0:10 ms 1:40 ms
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 87 of 183 ? 2016 dialog semiconductor register a d dress bit type label description r17 control_d 2:0 r/w twdscale 000: watchdog disabled 001: 1x scaling applied to twdmax period 010: 2x 011: 4x 100: 8x 101: 16x 110: 32x 111: 64x 3 r/w keepact_en 0: nonkey is enabled 1: nonkey is disabled, pin asserted to keepact (hw - assertion of bit watchdog) 4 r/w nonkey_sd 0: disables shutdown via nonkey 1: enables shutdown via nonkey 5 r/w gpi14_15_sd 0: disables shutdown via parallel assertion of gpi14 and gpi15 1: enables shutdown via gpi14 & gpi15 6 r/w acc_det_en enables acc_det circuitry when set to 1 7 r/w watchdog if set to 1 watchdog timer is reset. the bit is cleared back to 0 automatically. register a d dress bit t ype label description r18 pd_dis 0 r/w gpio_pd 0: gpio extender enabled during power - down 1: auto - disable of features configured as gpio pins during power - down mode and force the detection of a pending active state on gpis by re - enabling the pin through a passive state of the related gpi status register 1 r/w gp - adc_pd 0: adc/tsi measurements continue during power - down as configured 1: auto - disable auto measurements on a4, a5, a6, a7(tsi) and manual measurement on all channels during power - down mode; if no auto measurements for charging and on a0 are required switch off the adc completely 2 r/w pm - if_pd 0: power manager interface not disabled during power - down 1: auto - disable of power manager interface during power - down mode 3 r/w hs - 2 - wire _pd 0: hs - 2 - wire not disabled during power - down 1: auto - disable of hs - 2 - wire interface during power - down mode 4 r/w chg_pd 0: enables battery charging during power - down 1: auto - disable battery charging during power - down mode 5 r/w chg_bbat_pd 0: enables backup battery charger during power -
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 88 of 183 ? 2016 dialog semiconductor register a d dress bit t ype label description down mode 1: auto - disable backup battery charger during power - down 6 r/w out_32k_pd 0: enables out_32k during power - down 1: auto - disable out_32k output buffer during power - down mode and auto - enable during power - up from no - power mode when executing this id 7 r/w pm - cont_pd 0: sys_en, pwr_en, pwr1_en enabled during power - down 1: auto - disable of sys_en, pwr_en and pwr_en during power - down mode and force the detection of a pending active state by re - enabling the pin through a passive state of the related gpi status register register a d dress bit type label description r19 interface 0 r if_ type 0: power manager if is 4 - wire 1: power manager if is 2 - wire 1 r cpol 4 - wire if clock polarity 0: sk is low during idle 1: sk is high during idle 2 r cpha 4 - wire if clock phase (see table : 4 - wire clock configurations ) 3 r r/w_pol 4 - wire : read/write bit polarity 0: host indicates reading access via r/w bit = 0 1: host indicates reading access via r/w bit = 1 4 r ncs_pol 4 - wire chip select polarity 0: ncs is low active 1: ncs is high active 7:5 r if_base_addr ( note 1 ) 3 msb of 2 - wire control interfaces base address xxx10000 100 10000 = 0x90 write address of pm 2 - wire interface 100 10001 = 0x91 read address of pm 2 - wire interface 100 10010 = 0x92 write addre ss of hs - 2 - wire interface 100 10011 = 0x93 read address of hs - 2 - wire interface note 1 the base ad d ress can be written/modified for unmarked samples having the control otp_conf_lock not been asserted/fused . register a d dress bit type label description r20 reset 5:0 r/w reset_timer 000000: reset disabled 000001: 1.024 ms 000010: 2.048 ms 000011: 3.072 ms
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 89 of 183 ? 2016 dialog semiconductor register a d dress bit type label description 000100: 4.096 ms 000101: 5.120 ms . 011110: 30.720 ms 011111: 31.744 ms 100000: 32.768 ms 100001: 65.536 ms 100010: 98.304 ms .. 111101: 983.040 m s 111110: 1015.808 m s 111111: 1048.576 m s 7:6 r/w reset_event reset timer started by 00: ext_wakeup 01: sys_up 10: pwr_up 11: pwr1_up (internal signal)
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 90 of 183 ? 2016 dialog semiconductor 13 gpio e xtender the da9053 includes a gpio extender that offer up to 16 v ddout - tolerant (5.5 v max) general purpose input/output pins; each controlled by registers from the host. note the input voltage has to be lower than the vddio level selected for the port . the gpio ports are pin - shared with ports from gp - adc, tsi - interface, hs - 2 - wire interface and signals from the power manager and can be individually assigned. configuration settings and events from several gpix ports are shared with alternate features. for example, i f adcin5 was selected , overriding the configured thresholds will trigger a gpi 1 event that generates a maskable gpi1 interrupt. the gpi active high/low setting from gpiox_ type register and the selection of supply rail (and pull - up resistor) is also valid for the alternate port features selected via gpiox_pin ( for example sys_en, pwr _en and pwr1_en). the same is true for gpiox_mode to enable triggering a wake - up event (adcin4, adcin5, sys_en, pwr_en, pwr1_en, hs - 2 - wire interface) for the alternate features. in active and power - down mode the gpio extender can continuously monitor the level of ports that are selected as general purpose inputs. gpis are supplied from the internal rail vddcore or vdd_io2 and can be configured to trigger events in active high or active low mode. the input signals can be debounced or directly change the sta te of the assigned status register gpix to high or low. whenever the status has changed to its configured active state (edge sensitive) the assigned event register is set and the nirq signal is asserted (unless this nirq is masked inside the nirqmask regis ter). gpi 0, 3 to 11 and 13 to 15 will generate a system wake - up if debouncing is enabled. in debouncing off mode gpi 12 enables/disables ldo9, the minimum enable time is 100 s. the same feature is available at gpi 1 for ldo4_en and gpi 2 for ldo5_en. events on gpi10 can be used to control the progress of the power sequencer. processing id wait_step will cause the sequencer to wait until gpi 10 changes into active state. if defined as an output the gpo can be configured as open - drain or push - pull. the s upply rail can be individually selected from either vdd_io1 or vdd_io2. when selecting vdd_io1 in open - drain mode, there is an internal pull - up resistor against this rail, otherwise an external pull - up resistor towards the target voltage level is required. the output state will be assigned as configured by the gpio register bit gpiox_mode. gpo 10 and 11 are high - power gpo ports, where the maximum sink current is rated to be 15 ma and the maximum source current will be 4 ma. this enables driving leds with o ptional rtc timer controlled flashing. gpo 14 and 15 are high - power gpo ports able to sink up to 30 ma and include an optional pwm control. the pwm control can also be made to dim the brightness between its current value and a new value at a rate of 32 ms per step. in conjunction with the led3 drive, which offers a similar pwm mode, this creates a common anode tri - color led brightness control . register a d d ress bit type label description r21 gpio_0 - 1 1:0 r/w gpio0_pin pin assigned to 00: adcin4 01: gpi 10: gpo (open drain) 11: gpo (push - pull) 2 r/w gpio0_ type 0: gpi: active low gpo: supplied from vdd_io1/internal pull - up in
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 91 of 183 ? 2016 dialog semiconductor open - drain mode 1: gpi: active high gpo: supplied from vdd_io2/external pull - up in open - drain mode 3 r/w gpio0_ mode 0: gpi/adcin4: debouncing off gpo: sets output to low level 1: gpi/adcin4: debouncing on and generate wake - up gpo: sets output to high level 5:4 r/w gpio1_pin pin assigned to 00: adcin5/1.2 v comparator 01: gpi (ldo4 hw control) 10: gpo (open drain) 11: gpo (push - pull) 6 r/w gpio1_ type 0: gpi: active low gpo: supplied from vdd_io1/internal pull - up in open - drain mode 1: gpi: active high gpo: supplied from vdd_io2/external pull - up in open - drain mode 7 r/w gpio1_ mode 0: gpi/adcin5: / debouncing off, set ldo4_en when gpi transfers to active state (reset when gpi gets to passive state) 1.2 v comparator: (debouncing off), set ldo4_en when gpi transfers to active state (reset when gpi gets to passive state) gpo: sets output to low level 1 : gpi: debouncing on, no ldo4_en control adcin5 /1.2 v comparator : debouncing on and generate wake up gpo: sets output to high level if gpio1 pin = 01 and gpio1 mode = 00 then bit 1 of register r12 should also be set to avoid small nirq pulse generation . register a d d ress bit type label description r22 gpio_2 - 3 1:0 r/w gpio2_pin pin assigned to 00: adcin6 01: gpi (ldo5 hw control) 10: gpo (open drain) 11: gpo (push - pull) 2 r/w gpio2_ type 0: gpi: active low gpo: supplied from vdd_io1/internal pull - up in open - drain mode 1: gpi: active high gpo: supplied from vdd_io2/external pull - up in open - drain mode 3 r/w gpio2_mode 0: gpi/adcin6: (debouncing off), set ldo5_en when gpi transfers to active state (reset when gpi gets to passive state) gpo: sets output to low level
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 92 of 183 ? 2016 dialog semiconductor 1: gpi: debouncing on, no ldo5_en control adcin6: debouncing on and generate wake up gpo: sets output to high level 5:4 r/w gpio3_pin pin assigned to 00: tsiyn 01: gpi 10: gpo (open drain) 11: gpo (push - pull) 6 r/w gpio3_ type 0: gpi: active low gpo: supplied from vdd_io1/internal pull - up in open - drain mode 1: gpi: active high gpo: supplied from vdd_io2/external pull - up in open - drain mode 7 r/w gpio3_ mode 0: gpi: debouncing off gpo: sets output to low level 1: gpi: debouncing on and generate wake - up gpo: sets output to high level if gpio2 pin = 01 and gpio2 mode = 0 then bit 2 of register r12 should also be set to avoid small nirq pulse generation . register a d d ress bit type label description r23 gpio_4 - 5 1:0 r/w gpio4_pin pin assigned to 00: tsiyp 01: gpi 10: gpo (open drain) 11: gpo (push - pull) 2 r/w gpio4_ type 0: gpi: active low gpo: supplied from vdd_io1/internal pull - up in open - drain mode 1: gpi: active high gpo: supplied from vdd_io2/external pull - up in open - drain mode 3 r/w gpio4_ mode 0: gpi: debouncing off gpo: sets output to low level 1: gpi: debouncing on and generate wake - up gpo: sets output to high level 5:4 r/w gpio5_pin pin assigned to 00: tsixn 01: gpi 10: gpo (open drain) 11: gpo (push - pull) 6 r/w gpio5_ type 0: gpi: active low gpo: supplied from vdd_io1/internal pull - up in open - drain mode 1: gpi: active high gpo: supplied from vdd_io2/external pull - up in open - drain mode
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 93 of 183 ? 2016 dialog semiconductor 7 r/w gpio5_ mode 0: gpi: debouncing off gpo: sets output to low level 1: gpi: debouncing on and generate wake - up gpo: sets output to high level register a d d ress bit type label description r24 gpio_6 - 7 1:0 r/w gpio6_pin pin assigned to 00: tsixp 01: gpi 10: gpo (open drain) 11: gpo (push - pull) 2 r/w gpio6_ type 0: gpi: active low gpo: supplied from vdd_io1/internal pull - up in open - drain mode 1: gpi: active high gpo: supplied from vdd_io2/external pull - up in open - drain mode 3 r/w gpio6_ mode 0: gpi: debouncing off gpo: sets output to low level 1: gpi: debouncing on and generate wake - up gpo: sets output to high level 5:4 r/w gpio7_pin pin assigned to 00: tsiref 01: gpi 10: gpo (open drain) 11: gpo (push - pull) 6 r/w gpio7_ type 0: gpi: active low gpo: supplied from vdd_io1/internal pull - up in open - drain mode 1: gpi: active high gpo: supplied from vdd_io2/external pull - up in open - drain mode 7 r/w gpio7_ mode 0: gpi: debouncing off gpo: sets output to low level 1: gpi: debouncing on and generate wake - up gpo: sets output to high level register a d dress bit type label description r25 gpio_8 - 9 1:0 r/w gpio8_pin pin and status register bit assigned to 00: sys_en 01: gpi 10: gpo (open drain) 11: gpo (push - pull) 2 r/w gpio8_ type 0: gpi/sys_en: active low gpo: supplied from vdd_io1/internal pull - up in open - drain mode 1: gpi/sys_en: active high
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 94 of 183 ? 2016 dialog semiconductor gpo: supplied from vdd_io2/external pull - up in open - drain mode 3 r/w gpio8_ mode 0: gpi only (not sys_en): debouncing off gpo: sets output to low level 1: gpi/sys_en: debouncing on and generate wake - up gpo: sets output to high level 5:4 r/w gpio9_pin pin and status register bit assigned to 00: pwr_en 01: gpi 10: gpo (open drain) 11: gpo (push - pull) 6 r/w gpio9_ type 0: gpi/pwr_en: active low gpo: supplied from vdd_io1/internal pull - up in open - drain mode 1: gpi/pwr_en: active high gpo: supplied from vdd_io2/external pull - up in open - drain mode 7 r/w gpio9_ mode 0: gpi/pwr_en: debouncing off gpo: sets output to low level 1: gpi/pwr_en debouncing on and generate wake - up gpo: sets output to high level register a ddress bit type label description r26 gpio_10 - 11 1:0 r/w gpio10_pin pin and status register bit assigned to 00: pwr1_en 01: gpi 10: gpo (open drain) 11: gpo (push - pull)
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 95 of 183 ? 2016 dialog semiconductor 2 r/w gpio10_ type 0: gpi/pwr1_en: active low gpo: supplied from vdd_io1/internal pull - up in open - drain mode 1: gpi/pwr1_en: active high gpo: blinking from rtc counter, supplied from vdd_io2/ external pull - up in open - drain mode 3 r/w gpio10_ mode 0: gpi/pwr1_en: debouncing off gpo: sets output to low level 1: gpi/pwr1_en: debouncing on and generate wake - up, time out from processing id wait_step after 500ms gpo: sets output to high level 5:4 r/w gpio11_pin pin assigned to 00: acc_id_det 01: gpi 10: gpo (open drain) 11: gpo (push - pull) 6 r/w gpio11_ type 0: gpi: active low gpo: supplied from vdd_io1/internal pull - up in open - drain mode 1: gpi: active high gpo: blinking from rtc counter, supplied from vdd_io2/external pull - up in open - drain mode 7 r/w gpio11_ mode 0: gpi: : debouncing off / acc_id_det: debouncing off gpo: sets output to low level 1: gpi: : debouncing on and generate wake - up / acc_id_det: debouncing on and generate wake - up (for acc_id_det only at id_float falling edge) gpo: sets output to high level
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 96 of 183 ? 2016 dialog semiconductor register a d dress bit type label description r27 gpio_12 - 13 1:0 r/w gpio12_pin pin and status register bit assigned to 00: gp_fb1 (ext_wakeup/ready) 01: gpi (ldo9 hw control) 10: gpo (open drain) 11: gpo (push - pull) 2 r/w gpio12_ type 0: gpi: active low gpo/gp_fb1: supplied from vdd_io1/internal pull - up for open - drain 1: gpi: active high gpo/gp_fb1: supplied from vdd_io2/external pull - up in open - drain mode 3 r/w gpio12_mode 0: gpi: debouncing off , set ldo9_en when gpi transfers to active state (reset when gpi gets to passive state) gpo: sets output to low level 1: gpi: debouncing on, no ldo9_en control gpo: sets output to high level 5:4 r/w gpio13_pin pin assigned to 00: nvdd_fault 01: gpi 10: gpo (open drain) 11: gpo (push - pull) 6 r/w gpio13_ type 0: gpi: active low gpo/nvdd_fault: supplied from vdd_io1/internal pull - up for open - drain 1: gpi: active high gpo/nvdd_fault: supplied from vdd_io2/external pull - up in open - drain mode 7 r/w gpio13_mode 0: gpi: debouncing off gpo: sets output to low level 1: gpi: debouncing on and generate wake - up gpo: sets output to high level if gpio12 pin = 01 and gpio12 mode = 0 then bit 4 of register r13 should also be set to avoid small nirq pulse generation .
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 97 of 183 ? 2016 dialog semiconductor register a d dress bit type label description r28 gpio_14 - 15 1:0 r/w gpio14_pin pin assigned to 00: data (assigns gpio15_pin to clk) 01: gpi 10: gpo (open drain, pwm control) 11: gpo (push - pull) 2 r/w gpio14_ type 0: gpi: active low gpo: supplied from vdd_io1/internal pull - up in open - drain mode 1: gpi: active high gpo: supplied from vdd_io2/external pull - up in open - drain mode 3 r/w gpio14_ mode 0: gpi: debouncing off, no wake - up hs - 2 - wire : no wake - up gpo: sets output to low level 1: gpi:debouncing on and generate wake - up hs - 2 - wire : generate wake - up when interface was accessed gpo: sets output to high level 5 :4 r/w gpio15_pin pin assigned to 00: clk (see gpio14_pin) 01: gpi 10: gpo (open drain, pwm control) 11: gpo (push - pull) 6 r/w gpio15_ type 0: gpi: active low gpo: supplied from vdd_io1/internal pull - up in open - drain mode data/clk supplied from vdd_io1 ( note 1 ) 1: gpi: active high gpo: supplied from vdd_io2/external pull - up in open - drain mode data/clk supplied from vdd_io2 7 r/w gpio15_ mode 0: gpi: debouncing off gpo: sets output to low level 1: gpi: debouncing on and generate wake - up gpo: sets output to high level note 1 in power commander mode the hs - 2 - wire if is always supplied from vddcore .
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 98 of 183 ? 2016 dialog semiconductor 14 powe r supply s equencer the start - up of da9053 supplies is performed with a sequencer. the sequencer is able to control up to 22 ids (4 buck converter, 2 rail switches, 10 ldos, 4 feedback pin level controls, a wait id and a power - down register), which can be grouped in 3 power domains. the power sequences for each domain have configurable size. figure 43 : typical power - u p t iming n p o r _ u p p e r s y s _ u p p o w e r - u p p w r 1 _ e n s y s _ e n p w r _ e n e x t _ w a k e u p n o n k e y v d d c o r e v d d o u t 3 . 6 v ( f r o m c h a r g e r b u c k ) v d d r e f r e g i s t e r s l o a d e d f r o m o t p n v d d _ f a u l t s e q 1 s e q 2 s e q 3 w a i t f o r p w r _ e n p w r _ u p w a i t f o r p w r 1 _ e n d e b o u n c i n g ( 1 0 m s d e f a u l t ) n r e s e t s t a r t r e s e t t i m e o t p r e a d f i n i s h e d s e q 1 + s e q 2 + s e q 3 = 1 5 s t e p 1 m s t o 1 s w a i t f o r s y s _ e n = 3 2 u s
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 99 of 183 ? 2016 dialog semiconductor figure 44 : power m ode t ransitions n o p o w e r m o d e r e s e t m o d e p o w e r - d o w n m o d e d o m a i n s y s t e m d o m a i n p o w e r o t p r e a d ( w i t h 1 0 m s d e b o u n c i n g ) o t p r e a d ( w i t h 1 0 m s d e b o u n c i n g ) c h a r g e r p r o v i d e s v d d o u t o t p r e a d s u p p l i e s a n d s e q u e n c e r t i m e r e x t _ w a k e u p = 1 s y s _ u p = 1 p r o c e s s s e q u e n c e r i d s u p t o p o i n t e r s y s t e m _ e n d p r o c e s s s e q u e n c e r i d s d o w n t o p o i n t e r p a r t _ p o w n o r s t e p 0 s y s _ u p = 0 : n o s u p p l y i s p r e s e t 1 : s y s t e m s u p p l i e s a r e p r e s e t p w r _ u p = 1 p r o c e s s s e q u e n c e r i d s u p t o p o i n t e r p o w e r _ e n d w a k e u p e v e n t n o n k e y s y s _ e n , p w r _ e n , p w r 1 _ e n a s s e r t e d e _ g p i _ x ( i n c l . a d c t h r e s h o l d ) v o l t a g e c o m p a r a t o r 1 . 2 v p e n d o w n d e t e c t i o n i d _ f l o a t ( f a l l i n g e d g e ) v b u s / d c i n a t t a c h / r e m o v a l e n d o f b a t t e r y c h a r g i n g v d d o u t l o w w a r n i n g r t c a l a r m a c c e s s o f 2 - w i r e i f v d d o u t > v d d o u t _ m i n v d d c o r e > v p o r _ u p p e r v d d c o r e < v p o r _ l o w e r n v d d _ f a u l t o r v b a t _ o v e r o r t e m p _ o v e r o r t w d _ e r r o r o r n s d _ s h u t o r k e y _ s h u t o r w a i t _ s h u t a s s e r t e d s h u t d o w n = 1 ' p w r _ e n = 1 ' n v d d _ f a u l t o r v b a t _ o v e r o r t e m p _ o v e r o r t w d _ e r r o r o r n s d _ s h u t o r k e y _ s h u t o r w a i t _ s h u t a s s e r t e d s y s _ e n = 0 ' d e e p _ s l e e p = 1 ' s h u t d o w n = 1 ' p r o c e s s s e q u e n c e r i d s d o w n t o p o i n t e r s y s t e m _ e n d p w r _ u p = 0 : n o s u p p l y i s p r e s e t 1 : p o w e r s u p p l i e s a r e p r e s e t n v d d _ f a u l t o r v b a t _ o v e r o r t e m p _ o v e r o r t w d _ e r r o r o r n s d _ s h u t o r k e y _ s h u t o r w a i t _ s h u t a s s e r t e d s y s _ e n = 0 ' p w r _ e n = 0 ' d e e p _ s l e e p = 1 ' s h u t d o w n = 1 ' a c t i v e m o d e w a i t f o r ? a l i v e s i g n a l f r o m h o s t f i r s t w a t c h d o g ( i f e n a b l e d ) w a t c h d o g i n t i m e p r o c e s s s e q u e n c e r i d s u p t o p o i n t e r m a x _ c o u n t p w r 1 _ e n = 1 ' d o m a i n p o w e r 1 p r o c e s s s e q u e n c e r i d s d o w n t o p o i n t e r p o w e r _ e n d n v d d _ f a u l t o r v b a t _ o v e r o r t e m p _ o v e r o r t w d _ e r r o r o r n s d _ s h u t o r k e y _ s h u t o r w a i t _ s h u t a s s e r t e d s y s _ e n = 0 ' p w r _ e n = 0 ' p w r 1 _ e n = 0 ' d e e p _ s l e e p = 1 ' s h u t d o w n = 1 ' l d o c o r e b a n d - g a p 3 2 k o s c i l l a t o r b c d c o u n t e r v d d o u t , v b u s / d c i n _ p r o t a n d v d d c o r e c o m p a r a t o r s r e s e t s h u t d o w n a n d w a t c h d o g e x p i r e o v e r - t e m p e r a t u r e v d d c o r e c o m p a r a t o r s r e s e t f a u l t l o g a n d b c d - c o u n t e r l d o c o r e b a n d - g a p 3 2 k o s c i l l a t o r b c d c o u n t e r v d d o u t , v b u s / d c i n _ p r o t a n d v d d c o r e c o m p a r a t o r s s u p p l i e s w i t h p r e s e t v o l t a g e n o n - d i s a b l e d f e a t u r e s i n t e r n a l o s c i l l a t o r ( i f g p - a d c o r a b u c k i s e n a b l e d n o t i n s l e e p m o d e ) l d o c o r e b a n d - g a p 3 2 k o s c i l l a t o r b c d c o u n t e r v d d o u t , v b u s / d c i n _ p r o t a n d v d d c o r e c o m p a r a t o r s s u p p l i e s n o n - d i s a b l e d f e a t u r e s i n t e r n a l o s c i l l a t o r ( i f g p - a d c o r a b u c k i s e n a b l e d n o t i n s l e e p m o d e ) l d o c o r e b a n d - g a p 3 2 k o s c i l l a t o r b c d c o u n t e r v d d o u t , v b u s / d c i n _ p r o t a n d v d d c o r e c o m p a r a t o r s s u p p l i e s w a t c h d o g s u p e r v i s i o n ( i f e n a b l e d ) i n t e r n a l o s c i l l a t o r v d d o u t > v d d _ f a u l t _ u p p p e r p o w e r i n g d o w n p o w e r i n g u p v d d o u t > v d d _ f a u l t _ u p p p e r v d d o u t > v d d o u t _ m i n 1 2 8 m s t i m e o u t v b u s / d c i n > v c h _ t h r v b u s _ d e t / d c i n _ d e t r i s i n g n v d d _ f a u l t o r v b a t _ o v e r o r t e m p _ o v e r o r t w d _ e r r o r o r n s d _ s h u t o r k e y _ s h u t o r w a i t _ s h u t a s s e r t e d s y s _ e n = 0 ' p w r _ e n = 0 ' d e e p _ s l e e p = 1 ' s h u t d o w n = 1 ' e x t _ w a k e u p = 0
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 100 of 183 ? 2016 dialog semiconductor table 48 : power s equencer c ontrol r egisters register a d dress bit type label description r29 id_0_1 0 r/w nres_mode 0: no assertion of nreset during power - down mode 1: assert nreset when entering power - down mode (release after leaving power - down mode) 1 r/w def_supply when asserted all supplies (beside ldocore) are enabled/disabled from otp default mode 2 r/w sys_pre 0: set sys_up as configured from supplies presettings 1: always de - assert sys_up before powering down domain system 3 r/w wait_id_always pd_mode 0: only perform the wait_id step on first use of the sequencer 1: perform the wait_id step all uses of the sequencer 7:4 r/w ldo1_step power sequencer time slot 9 register a d dress bit type label description r30 id_2_3 3:0 r/w ldo2_step power sequencer time slot 4 7:4 r/w ldo3_step power sequencer time slot 8 register a d dress bit type label description r31 id_4_5 3:0 r/w ldo4_step power sequencer time slot 2 7:4 r/w ldo5_step power sequencer time slot 3 register a d dress bit type label description r32 id_6_7 3:0 r/w ldo6_step not controlled by power sequencer 7:4 r/w ldo7_step not controlled by power sequencer register a d dress bit type label description r33 id_8_9 3:0 r/w ldo8_step not controlled by power sequencer 7:4 r/w ldo9_step not controlled by power sequencer
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 101 of 183 ? 2016 dialog semiconductor register a d d ress bit type label description r34 id_10_11 3:0 r/w ldo10_step not controlled by power sequencer 7:4 r/w pd_dis_step power sequencer time slot 5 register a d d ress bit type label description r35 id_12_13 3:0 r/w vperi_sw_step not controlled by power sequencer 7:4 r/w vmem_sw_step not controlled by power sequencer register a d dress bit type label description r36 id_14_15 3:0 r/w buckcore_step power sequencer time slot 1 7:4 r/w buckpro_step power sequencer time slot 7 register a a d dress bit type label description r37 id_16_17 3:0 r/w buckmem_step not controlled by power sequencer 7:4 r/w buckperi_step not controlled by power sequencer register a d dress bit type label description r38 id_18_19 3:0 r/w gp_rise1_step not controlled by power sequencer 7:4 r/w gp_rise2_step not controlled by power sequencer register a d dress bit type label description r39 id_20_21 3:0 r/w gp_fall1_step not controlled by power sequencer 7:4 r/w gp_fall2_step not controlled by power sequencer register a d dress bit type label description r40 seq_status 3:0 r/w wait_step not controlled by power sequencer 7:4 r/w seq_pointer actual pointer position (time slot) of power sequencer
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 102 of 183 ? 2016 dialog semiconductor register a d dress bit t ype label description r41 seq_a 3:0 r/w system_end otp pointer to last supply of domain system 7:4 r/w power_end otp pointer to last supply of domain power register a d d ress bit type label description r42 seq_b 3:0 r/w max_count otp pointer to last supply of domain power1 7:4 r/w part_down otp pointer for partial power - down mode register a d d ress bit t ype label description r43 seq_timer 3:0 r/w seq_time 0000: 32 s 0001: 64 s 0010: 96 s 0011: 128 s 0100: 160 s 0101: 192 s 0110: 224 s 0111: 256 s 1000: 288 s 1001: 384 s 1010: 448 s 1011: 512 s 1100: 1.024 ms 1101: 2.048 ms 1110: 4.096 ms 1111: 8.192 ms 7:4 r/w seq_dummy 0000: 32 s 0001: 64 s 0010: 96 s 0011: 128 s 0100: 160 s 0101: 192 s 0110: 224 s 0111: 256 s 1000: 288 s 1001: 384 s 1010: 448 s 1011: 512 s 1100: 1.024 ms 1101: 2.048 ms 1110: 4.096 ms 1111: 8.192 ms
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 103 of 183 ? 2016 dialog semiconductor
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 104 of 183 ? 2016 dialog semiconductor 15 voltage r egulators three types of low dropout regulators are integr ated on the da9053, each optimiz ed for performance depending on the most critical parameter of the circuitry supplied. for high performance analog supplies ( for example audio) the regulators have been designed to offer high psrr and low noise, for the digital supplies psrr is relaxed saving quiescent current and for the pmic core/rtc supplies quiescent current has been optimised as the most important performance paramete rs. the regulators employ dialog semiconductors smartmirror ? dynamic biasi ng, removing the need for a low - power operating mode and associated software or hardware overhead. smartmirror? technology guarantees a high phase margin within the regulator cont rol loop and has been designed to offer stable performance with small output capacitances over a wide range of output currents. the circuit technique offers significantly higher gain bandwidth performance than conventional designs, enabling higher power su pply rejection performance at higher frequencies. psrr is also maintained across the full operating current range however quiescent current consumption is scaled to demand giving improved efficiency when current demand is low. figure 45 : smart mirror tm v oltage r egulator the regulator output voltages are fully programmable via the control interface allowing optimisation of the complete system for maximum performance and power efficiency. for security reasons the re - programming of o utput voltages from the control interfaces can be disabled. the default output voltage is loaded from after start - up from otp. a power saving mode is not required for the ldos due to the use of dynamic biasing in the ldo internal circuitry, so when operati ng at low current demands the quiescent current taken by the regulator is automatically minimised. ld01 to ldo10
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 105 of 183 ? 2016 dialog semiconductor can optionally be supplied from a buck output (vdd < 2.8 v). in this mode some specification parameters will change. ldo2 and ldo3 include dynamic dvc control to enable power savings on peripheral domains: the output voltage is programmable over the power manager bus in 25 mv steps. the output voltage ramp step size is 6.25 mv/ s while slewing. if the feedback signal is configured to be read y this line is asserted while slewing. note powering down to reset mode will automatically disable all regulators beside ldo1. ldo4, 5 and 9 include an optional hardware enable/disable via gpio1, 2 and 12 by selecting the gpi feature with debouncing off. ldo1 to ldo10 can be controlled inside the power manager sequence. if enabled at sequencer step 0 (def_supply) supplies can be default enabled via otp whenever the sequencer passes step 0 (otp se ttings are used). to limit the battery rush current it is recommended to enable not more than a single supply (including bucks) at step 0 . when powering down ( for example to power - down mode) sequencer controlled supplies can be pre - configured with a new ta rget voltage (ldox_conf bit is set). if ldox_conf was asserted in parallel with ldox_en also the supply enable is deferred until the sequencer is processing the related id. the previous output voltage and enable state will be kept unchanged until the seque ncer processes the related time slot/id during powering down (ignoring any assertions of vldox_go while ldox_conf is high). before wake - up from power - down mode (processing time slots from domain system) the sequencer will configure all regulators with thei r default voltage values from otp and by that also reset the ldox_conf bits. the regulators can also be enabled/disabled/configured via the power manager and hs - 2 - wire interface when the da9053 is in the active state. voltage transitions on ldos including dvc will always be ramped. disabling regulators ldo1, 2, and 5 can switch off their pull down resistor which is required for usage in parallel to an alternate supply. 15.1 c ore r egulator ldocore the ldocore will be used for running the da9053 internal real time clock module, internal state machine, gpio pins with comparators, bias, reference, gpadc, otp and power manager regist e rs. it is supplied by the battery switch either from an external supply, vbat or the backup battery (coin cell or super cap). if no back up battery exists or the backup battery charger is configured to a level below 2.0 v the automatic vref switch to the backup battery can be disabled. 15.2 dc/dc b uck c onverters da9053 includes four dc/dc b uck converters, note powering down to reset mode will automatically disable all buck converters.
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 106 of 183 ? 2016 dialog semiconductor figure 46 : dcdc b uck c onverter 15.3 converters buckcore, buckpro and buckmem with dvc these converters are high efficiency synchronous step down regulators operating at a high frequency (2 mhz) supplying individual output voltages with +/ - 3 % accuracy. default output voltage is loaded from otp and can be set in 25 mv steps. the dvc controller allows the following features: the buck converter output voltage to be programmable over the power manager bus in 25 mv steps. the output voltage ramp step size is 6.25 mv/ s while slewing. if the feedback signal is configured to be ready this line is asserted while slewing. output voltages below 0.725 v will only be supported in pulse f requency m odulat ion (pfm) mode. during a voltage reduction below 0.725 v the slew rate control ends at 0.725 v and the buck mode is automatically changed to sleep mode (with reduced maximum current capability). the timing of voltage transitions between 0.5 v and 0.725 v d epends on the load. the supply current during pwm (synchronous rectification) operation is in the order of 4 ma for buckcore and 2.5 ma for buckpro, buckmem and buckperi (quiescent current and charge/discharge current) and drops to < 1 a in shutdown. the b uck converter can be forced to operate in either synchronous mode o r sleep mode. additionally the b uck converter has an automatic mode where it will switch between synchronous and sleep mode depending on the load current. in sleep mode the buck converter works in pfm mode. an internal zero crossing comparator is used to time the turn - off of the nfet, thereby removing the need for an external schottky diode. the converters buckperi and buckmem provide additional power path switches that can be controlled f rom the sequencer. this enables a partial power down of io and power rails for optimized application quiescent currents during standby/hibernate modes. the embedded soft start (approx imately 200 s) enables a usage as power manager controlled hot swap power switches with a maximum capacitive load up to 10 f ( for example for sd - cards). if a switch is open, the associated pin will be discharged to vss by a pull down resistor. d c d c c o n v e r t e r ( 2 m h z ) d r v c t r l v b u c k v f b i s e n s e c o u t c n t r l v d d ( 2 . 8 . . . 5 . 0 v ) s l e e p _ e n d a c r e f p o w e r - e n 2 . 2 u h
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 107 of 183 ? 2016 dialog semiconductor figure 47 : buckperi / buckmem output s witches table 49 shows the relationship between the programmed buck current limit and the saturation current limit of the coil. it must be ensured that the mi nimum i sat is above the maximum current limit including spread . table 49 : b uck current l imit and c oil saturation current l imit min. i sat (ma) frequency (mhz) buck current l imit (ma) 3600 2 3000 2900 2 2400 1800 2 1500 1680 2 1400 1450 2 1200 1080 2 900 840 2 700 v b u c k p e r i / v b u c k m e m s w b u c k p e r i / s w b u c k m e m v p e r i _ s w / v m e m _ s w s e q u e n c e r c o n t r o l l e d p o w e r d o w n s w i t c h e s r o n < 0 . 5 o h m > 1 0 u f < 1 0 u f
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 108 of 183 ? 2016 dialog semiconductor 16 power s upplies table 50 : power supply control r egisters register a d dress bit type label description r44 buck_a 1:0 r/w bcore_mode 00: buckcore always operates in sleep mode 01: buckcore operates in automatic mode 10: buckcore always operates in synchronous mode 11: buckcore in automatic forcing to synchronous mode 3:2 r/w bcore_ilim 00: buckcore current limit 1600 ma 01: buckcore current limit 2000 ma 10: buckcore current limit 2400 ma 11: buckcore current limit 3000 ma 5:4 r/w bpro_mode 00: buckpro always operates in sleep mode 01: buckpro operates in automatic mode 10: buckpro always operates in synchronous mode 11: buckpro in automatic forcing to synchronous mode 7:6 r/w bpro_ilim 00: buckpro current limit 800 ma 01: buckpro current limit 1000 ma 10: buckpro current limit 1200 ma 11: buckpro current limit 1500 ma register a d d ress bit type label description r45 buck_b 1:0 r/w bmem_ mode 00: buckmem always operates in sleep mode 01: buckmem operates in automatic mode 10: buckmem always operates in synchronous mode 11: buckmem in automatic forcing to synchronous mode 3:2 r/w bmem_ilim 00: buckmem current limit 800 ma 01: buckmem current limit 1000 ma 10: buckmem current limit 1200 ma 11: buckmem current limit 1500 ma 5:4 r/w bperi_ mode 00: buckperi always operates in sleep mode 01: buckperi operates in automatic mode 10: buckperi always operates in synchronous mode 11: buckperi in automatic forcing to synchronous mode 7:6 r/w bperi_ilim 00: buckperi current limit 800 ma 01: buckperi current limit 1000 ma 10: buckperi current limit 1200 ma 11: buckperi current limit 1500 ma
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 109 of 183 ? 2016 dialog semiconductor register a d dress bit t ype label description r46 buckcore 5:0 r/w vbcore 000000: 0.500 v 000001: 0.525 v 000010: 0.550 v 000011: 0.575 v 000100: 0.600 v 000101: 0.625 v 011011: 1.175 v 011100: 1.200 v 011101: 1.225 v 011110: 1.250 v 011111: 1.275 v 100000: 1.300 v 100001: 1.325 v 100010: 1.350 v 100011: 1.375 v 100100: 1.400 v 100101: 1.425 v 100110: 1.450 v 100111: 1.475 v 101000: 1.500 v 101001: 1.525 v 101010: 1.550 v 101011: 1.575 v 101100: 1.600 v 101101: 1.625 v 101110: 1.650 v 101111: 1.675 v 110000: 1.700 v 110001: 1.725 v 110010: 1.750 v 110011: 1.775 v 110100: 1.800 v 110101: 1.825 v 110110: 1.850 v 110111: 1.875 v 111000: 1.900 v 111001: 1.925 v 111010: 1.950 v 111011: 1.975 v 111100: 2.000 v 111101: 2.025 v 111110: 2.050 v 111111: 2.075 v 6 r/w bcore_en 0: buckcore disabled
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 110 of 183 ? 2016 dialog semiconductor 1: buckcore enabled 7 r/w bcore_conf 0: voltage ramped after assertion of vb_core_go 1: supply voltage preset register a d dress bit type label description r47 buckpro 5:0 r/w vbpro 000000: 0.500 v 000001: 0.525 v 000010: 0.550 v 000011: 0.575 v 000100: 0.600 v 000101: 0.625 v 011011: 1.175 v 011100: 1.200 v 011101: 1.225 v 011110: 1.250 v 011111: 1.275 v 100000: 1.300 v 100001: 1.325 v 100010: 1.350 v 100011: 1.375 v 100100: 1.400 v 100101: 1.425 v 100110: 1.450 v 100111: 1.475 v 101000: 1.500 v 101001: 1.525 v 101010: 1.550 v 101011: 1.575 v 101100: 1.600 v 101101: 1.625 v 101110: 1.650 v 101111: 1.675 v 110000: 1.700 v 110001: 1.725 v 110010: 1.750 v 110011: 1.775 v 110100: 1.800 v 110101: 1.825 v 110110: 1.850 v 110111: 1.875 v 111000: 1.900 v 111001: 1.925 v 111010: 1.950 v 111011: 1.975 v 111100: 2.000 v
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 111 of 183 ? 2016 dialog semiconductor 111101: 2.025 v 111110: 2.050 v 111111: 2.075 v 6 r/w bpro_en 0: buckpro disabled 1: buck pro enabled 7 r/w bpro_conf 0: voltage ramped after assertion of vb_pro_go 1: supply voltage preset register a d dress bit t ype label description r48 buckmem 5:0 r/w vbmem 000000: 0.950 v 000001: 0.975 v 000010: 1.000 v 000011: 1.025 v 000100: 1.050 v 010110: 1.500 v 010111: 1.525 v 011000: 1.550 v 011001: 1.575 v 011010: 1.600 v 011011: 1.625 v 011100: 1.650 v 011101: 1.675 v 011110: 1.700 v 011111: 1.725 v 100000: 1.750 v 100001: 1.775 v 100010: 1.800 v 100011: 1.825 v 100100: 1.850 v 100101: 1.875 v 100110: 1.900 v 100111: 1.925 v 101000: 1.950 v 101001: 1.975 v 101010: 2.000 v 101011: 2.025 v 101100: 2.050 v 101101: 2.075 v 101110: 2.100 v 101111: 2.125 v 110000: 2.150 v 110001: 2.175 v 110010: 2.200 v 110011: 2.225 v 110100: 2.250 v
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 112 of 183 ? 2016 dialog semiconductor 110101: 2.275 v 110110: 2.300 v 110111: 2.325 v 111000: 2.350 v 111001: 2.375 v 111010: 2.400 v 111011: 2.425 v 111100: 2.450 v 111101: 2.475 v 111110: 2.500 v 111111: 2.525 v 6 r/w bmem_en 0: buckmem disabled 1: buckmem enabled 7 r/w bmem_conf 0: voltage ramped after assertion of vb_mem_go 1: supply voltage preset register a d dress bit t ype label description r49 buckperi 5:0 r/w vbperi 000000: 0.950 v 000001: 0.975 v 000010: 1.000 v 000011: 1.025 v 000100: 1.050 v 010110: 1.500 v 010111: 1.525 v 011000: 1.550 v 011001: 1.575 v 011010: 1.600 v 011011: 1.625 v 011100: 1.650 v 011101: 1.675 v 011110: 1.700 v 011111: 1.725 v 100000: 1.750 v 100001: 1.775 v 100010: 1.800 v 100011: 1.825 v 100100: 1.850 v 100101: 1.875 v 100110: 1.900 v 100111: 1.925 v 101000: 1.950 v 101001: 1.975 v 101010: 2.000 v 101011: 2.025 v 101100: 2.050 v
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 113 of 183 ? 2016 dialog semiconductor 101101: 2.075 v 101110: 2.100 v 101111: 2.125 v 110000: 2.150 v 110001: 2.175 v 110010: 2.200 v 110011: 2.225 v 110100: 2.250 v 110101: 2.275 v 110110: 2.300 v 110111: 2.325 v 111000: 2.350 v 111001: 2.375 v 111010: 2.400 v 111011: 2.425 v 111100: 2.450 v 111101: 2.475 v 111110: 2.500 v 111111: 2.525 v 6 r/w bperi_en 0: buckperi disabled 1: buckperi enabled 7 r/w bperi_conf 0: supply voltage immediate change 1: supply voltage preset (activated during power down sequence instead of disable) register a d dress bit t ype label description r50 ldo1 4:0 r/w vldo1 00000: 0.600 v 00001: 0.650 v 00010: 0.700 v 00011: 0.750 v 00100: 0.800 v 00101: 0.850 v 00110: 0.900 v 00111: 0.950 v 01000: 1.000 v 01001: 1.050 v 01010: 1.100 v 01011: 1.150 v 01100: 1.200 v 01101: 1.250 v 01110: 1.300 v 01111: 1.350 v 10000: 1.400 v 10001: 1 .450 v 10010: 1.500 v 10011: 1.550 v
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 114 of 183 ? 2016 dialog semiconductor 10100: 1.600 v 10101: 1.650 v 10110: 1.700 v 10111: 1.750 v 11000: 1.800 v >11000: 1.800 v 5 r reserved 6 r/w ldo1_en 0: ldo1 disabled 1: ldo1 enabled 7 r/w ldo1_conf 0: supply voltage immediate change 1: supply voltage preset (activated during power down sequence instead of disable) register a d dress bit t ype label description r51 ldo2 5:0 r/w vldo2 000000: 0.600 v 000001: 0.625 v 000010: 0.650 v 000011: 0.675 v 000100: 0.700 v 000101: 0.725 v 000110: 0.750 v 000111: 0.775 v 001000: 0.800 v 001001: 0.825 v 001010: 0.850 v 001011: 0.875 v 001100: 0.900 v 001101: 0.925 v 001110: 0.950 v 001111: 0.975 v 010000: 1.000 v 010001: 1.025 v 010010: 1.050 v 010011: 1.075 v 010100: 1.100 v 010101: 1.125 v 010110: 1.150 v 010111: 1.175 v 011000: 1.200 v 011001: 1.225 v 011010: 1.250 v 011011: 1.275 v 011100: 1.300 v 011101: 1.325 v 011110: 1.350 v 011111: 1.375 v
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 115 of 183 ? 2016 dialog semiconductor register a d dress bit t ype label description 100000: 1.400 v 100001: 1.425 v 100010: 1.450 v 100011: 1.475 v 100100: 1.500 v 100101: 1.525 v 100110: 1.550 v 100111: 1.575 v 101000: 1.600 v 101001: 1.625 v 101010: 1.650 v 101011: 1.675 v 101100: 1.700 v 101101: 1.725 v 101110: 1.750 v 101111: 1.775 v 110000: 1.800 v >110000: 1.800 v 6 r/w ldo2_en 0: ldo2 disabled 1: ldo2 enabled 7 r/w ldo2_conf 0: voltage ramped after assertion of vldo2_go 1: supply voltage preset (ramping activated during power down) register a d dress bit t ype label description r52 ldo3 5:0 r/w vldo3 000000: 1.725 v 000001: 1.750 v 000010: 1.775 v 000011: 1.800 v 000100: 1.825 v 010110: 2.275 v 010111: 2.300 v 011000: 2.325 v 011001: 2.350 v 011010: 2.375 v 011011: 2.400 v 011100: 2.425 v 011101: 2.450 v 011110: 2.475 v 011111: 2.500 v 100000: 2.525 v 100001: 2.550 v 100010: 2.575 v
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 116 of 183 ? 2016 dialog semiconductor register a d dress bit t ype label description 100011: 2.600 v 100100: 2.625 v 100101: 2.650 v 100110: 2.675 v 100111: 2.700 v 101000: 2.725 v 101001: 2.750 v 101010: 2.775 v 101011: 2.800 v 101100: 2.825 v 101101: 2.850 v 101110: 2.875 v 101111: 2.900 v 110000: 2.925 v 110001: 2.950 v 110010: 2.975 v 110011: 3.000 v 110100: 3.025 v 110101: 3.050 v 110110: 3.075 v 110111: 3.100 v 111000: 3.125 v 111001: 3.150 v 111010: 3.175 v 111011: 3.200 v 111100: 3.225 v 111101: 3.250 v 111110: 3.275 v 111111: 3.300 v 6 r/w ldo3_en 0: ldo3 disabled 1: ldo3 enabled 7 r/w ldo3_conf 0: voltage ramped after assertion of vldo3_go 1: supply voltage preset register a d dress bit t ype label description r53 ldo4 5:0 r/w vldo4 000000: 1.725 v 000001: 1.750 v 000010: 1.775 v 000011: 1.800 v 000100: 1.825 v 010110: 2.275 v 010111: 2.300 v 011000: 2.325 v
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 117 of 183 ? 2016 dialog semiconductor register a d dress bit t ype label description 011001: 2.350 v 011010: 2.375 v 011011: 2.400 v 011100: 2.425 v 011101: 2.450 v 011110: 2.475 v 011111: 2.500 v 100000: 2.525 v 100001: 2.550 v 100010: 2.575 v 100011: 2.600 v 100100: 2.625 v 100101: 2.650 v 100110: 2.675 v 100111: 2.700 v 101000: 2.725 v 101001: 2.750 v 101010: 2.775 v 101011: 2.800 v 101100: 2.825 v 101101: 2.850 v 101110: 2.875 v 101111: 2.900 v 110000: 2.925 v 110001: 2.950 v 110010: 2.975 v 110011: 3.000 v 110100: 3.025 v 110101: 3.050 v 110110: 3.075 v 110111: 3.100 v 111000: 3.125 v 111001: 3.150 v 111010: 3.175 v 111011: 3.200 v 111100: 3.225 v 111101: 3.250 v 111110: 3.275 v 111111: 3.300 v 6 r/w ldo4_en 0: ldo4 disabled 1: ldo4 enabled 7 r/w ldo4_conf 0: supply voltage immediate change 1: supply voltage preset (activated during power down sequence instead of disable)
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 118 of 183 ? 2016 dialog semiconductor register a d dress bit t ype label description r54 ldo5 5:0 r/w vldo5 000000: 1.20 v 000001: 1.25 v 000010: 1.30 v 000011: 1.35 v 000100: 1.40 v 000101: 1.45 v 000110: 1.50 v 000111: 1.55 v 001000: 1.60 v 001001: 1.65 v 001010: 1.70 v 001011: 1.75 v 001100: 1.80 v 001101: 1.85 v 001110: 1.90 v 001111: 1.95 v 010000: 2.00 v 010001: 2.05 v 010010: 2.10 v 010011: 2.15 v 010100: 2.20 v 010101: 2.25 v 010110: 2.30 v 010111: 2.35 v 011000: 2.40 v 011001: 2.45 v 011010: 2.50 v 011011: 2.55 v 011100: 2.60 v 011101: 2.65 v 011110: 2.70 v 011111: 2.75 v 100000: 2.80 v 100001: 2.85 v 100010: 2.90 v 100011: 2.95 v 100100: 3.00 v 100101: 3.05 v 100110: 3.10 v 100111: 3.15 v 101000: 3.20 v 101001: 3.25 v 101010: 3.30 v 101011: 3.35 v 1 01100: 3.40 v 101101: 3.45 v 101110: 3.50 v
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 119 of 183 ? 2016 dialog semiconductor 101111: 3.55 v 110000: 3.60 v >110000: 3.60 v 6 r/w ldo5_en 0: ldo5 disabled 1: ldo5 enabled 7 r/w ldo5_conf 0: supply voltage immediate change 1: supply voltage preset (activated during power down sequence instead of disable) register a d dress bit t ype label description r55 ldo6 5:0 r/w vldo6 000000: 1.20 v 000001: 1.25 v 000010: 1.30 v 000011: 1.35 v 000100: 1.40 v 000101: 1.45 v 000110: 1.50 v 000111: 1.55 v 001000: 1.60 v 001001: 1.65 v 001010: 1.70 v 001011: 1.75 v 001100: 1.80 v 001101: 1.85 v 001110: 1.90 v 001111: 1.95 v 010000: 2.00 v 010001: 2.05 v 010010: 2.10 v 010011: 2.15 v 010100: 2.20 v 010101: 2.25 v 010110: 2.30 v 010111: 2.35 v 011000: 2.40 v 011001: 2.45 v 011010: 2.50 v 011011: 2.55 v 011100: 2.60 v 011101: 2.65 v 011110: 2.70 v 011111: 2.75 v 100000: 2.80 v 100001: 2.85 v 100010: 2.90 v 100011: 2.95 v
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 120 of 183 ? 2016 dialog semiconductor register a d dress bit t ype label description 100100: 3.00 v 100101: 3.05 v 100110: 3.10 v 100111: 3.15 v 101000: 3.20 v 101001: 3.25 v 101010: 3.30 v 101011: 3.35 v 101100: 3.40 v 1 01101: 3.45 v 101110: 3.50 v 101111: 3.55 v 110000: 3.60 v >110000: 3.60 v 6 r/w ldo6_en 0: ldo6 disabled 1: ldo6 enabled 7 r/w ldo6_conf 0: supply voltage immediate change 1: supply voltage preset (activated during power down sequence instead of disable) register a d dress bit t ype label description r56 ldo7 5:0 r/w vldo7 000000: 1.20 v 000001: 1.25 v 000010: 1.30 v 000011: 1.35 v 000100: 1.40 v 000101: 1.45 v 000110: 1.50 v 000111: 1.55 v 001000: 1.60 v 001001: 1.65 v 001010: 1.70 v 001011: 1.75 v 001100: 1.80 v 001101: 1.85 v 001110: 1.90 v 001111: 1.95 v 010000: 2.00 v 010001: 2.05 v 010010: 2.10 v 010011: 2.15 v 010100: 2.20 v 010101: 2.25 v 010110: 2.30 v
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 121 of 183 ? 2016 dialog semiconductor register a d dress bit t ype label description 010111: 2.35 v 011000: 2.40 v 011001: 2.45 v 011010: 2.50 v 011011: 2.55 v 011100: 2.60 v 011101: 2.65 v 011110: 2.70 v 011111: 2.75 v 100000: 2.80 v 100001: 2.85 v 100010: 2.90 v 100011: 2.95 v 100100: 3.00 v 100101: 3.05 v 100110: 3.10 v 100111: 3.15 v 101000: 3.20 v 101001: 3.25 v 101010: 3.30 v 101011: 3.35 v 101100: 3.40 v 101101: 3 .45 v 101110: 3.50 v 101111: 3.55 v 110000: 3.60 v >110000: 3.60 v 6 r/w ldo7_en 0: ldo7 disabled 1: ldo7 enabled 7 r/w ldo7_conf 0: supply voltage immediate change 1: supply voltage preset (activated during power down sequence instead of disable) register a d dress bit t ype label description r57 ldo8 5:0 r/w vldo8 000000: 1.20 v 000001: 1.25 v 000010: 1.30 v 000011: 1.35 v 000100: 1.40 v 000101: 1.45 v 000110: 1.50 v 000111: 1.55 v 001000: 1.60 v 001001: 1.65 v
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 122 of 183 ? 2016 dialog semiconductor register a d dress bit t ype label description 001010: 1.70 v 001011: 1.75 v 001100: 1.80 v 001101: 1.85 v 001110: 1.90 v 001111: 1.95 v 010000: 2.00 v 010001: 2.05 v 010010: 2.10 v 010011: 2.15 v 010100: 2.20 v 010101: 2.25 v 010110: 2.30 v 010111: 2.35 v 011000: 2.40 v 011001: 2.45 v 011010: 2.50 v 011011: 2.55 v 011100: 2.60 v 011101: 2.65 v 011110: 2.70 v 011111: 2.75 v 100000: 2.80 v 100001: 2.85 v 100010: 2.90 v 100011: 2.95 v 100100: 3.00 v 100101: 3.05 v 100110: 3.10 v 100111: 3.15 v 101000: 3.20 v 101001: 3.25 v 101010: 3.30 v 101011: 3.35 v 101100: 3.40 v 101101: 3.45 v 101110: 3 .50 v 101111: 3.55 v 110000: 3.60 v >110000: 3.60 v 6 r/w ldo8_en 0: ldo8 disabled 1: ldo8 enabled 7 r/w ldo8_conf 0: supply voltage immediate change 1: supply voltage preset (activated during power down sequence instead of disable)
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 123 of 183 ? 2016 dialog semiconductor register a d dress bit t ype label description r58 ldo9 5:0 r/w vldo9 000000: 1.25 v 000001: 1.30 v 000010: 1.35 v 000011: 1.40 v 000100: 1.45 v 000101: 1.50 v 000110: 1.55 v 000111: 1.60 v 001000: 1.66 v 001001: 1.70 v 001010: 1.75 v 001011: 1.80 v 001100: 1.85 v 001101: 1.90 v 001110: 1.95 v 001111: 2.00 v 010000: 2.05 v 010001: 2.10 v 010010: 2.15 v 010011: 2.20 v 010100: 2.25 v 010101: 2.30 v 010110: 2.35 v 010111: 2.40 v 011000: 2.45 v 011001: 2.50 v 011010: 2.55 v 011011: 2.60 v 011100: 2.65 v 011101: 2.70 v 011110: 2.75 v 011111: 2.80 v 100000: 2.85 v 100001: 2.90 v 100010: 2.95 v 100011: 3.00 v 100100: 3.05 v 100101: 3.10 v 100110: 3.15 v 100111: 3.20 v 101000: 3.25 v 101001: 3.30 v 101010: 3.35 v 101011: 3.40 v 101100: 3.45 v 101101: 3.50 v 101110: 3.55 v
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 124 of 183 ? 2016 dialog semiconductor 101111: 3 .60 v 110000: 3.65 v >110000: 3.65 v 6 r/w ldo9_en 0: ldo9 disabled 1: ldo9 enabled 7 r/w ldo9_conf 0: supply voltage immediate change 1: supply voltage preset (activated during power down sequence instead of disable) register a d dress bit t ype label description r59 ldo10 5:0 r/w vldo10 000000: 1.20 v 000001: 1.25 v 000010: 1.30 v 000011: 1.35 v 000100: 1.40 v 000101: 1.45 v 000110: 1.50 v 000111: 1.55 v 001000: 1.60 v 001001: 1.65 v 001010: 1.70 v 001011: 1.75 v 001100: 1.80 v 001101: 1.85 v 001110: 1.90 v 001111: 1.95 v 010000: 2.00 v 010001: 2.05 v 010010: 2.10 v 010011: 2.15 v 010100: 2.20 v 010101: 2.25 v 010110: 2.30 v 010111: 2.35 v 011000: 2.40 v 011001: 2.45 v 011010: 2.50 v 011011: 2.55 v 011100: 2.60 v 011101: 2.65 v 011110: 2.70 v 011111: 2.75 v 100000: 2.80 v 100001: 2.85 v 100010: 2.90 v 100011: 2.95 v
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 125 of 183 ? 2016 dialog semiconductor register a d dress bit t ype label description 100100: 3.00 v 100101: 3.05 v 100110: 3.10 v 100111: 3.15 v 101000: 3.20 v 101001: 3.25 v 101010: 3.30 v 101011: 3.35 v 101100: 3.40 v 101101: 3.45 v 101110: 3.50 v 101111: 3.55 v 110000: 3.60 v >110000: 3.60 v 6 r/w ldo10_en 0: ldo10 disabled 1: ldo10 enabled 7 r/w ldo10_conf 0: supply voltage immediate change 1: supply voltage preset (activated during power down sequence instead of disable) register a d dress bit t ype label description r60 supply 0 r/w vb_core_go 0: hold vbuckcore at current setting. 1: ramp buckcore to configured voltage. while the voltage is ramping, write access is blocked to buckpro register. vbuckcore_go is cleared when the target voltage is reached. while ramping, the buck is forced into pwm 1 r/w vb_pro_go 0: hold vbuckpro at current setting. 1: ramp buckpro to configured voltage. while the voltage is ramping, write access is blocked to buckpro register. vbuckpro_go is cleared when the target volta ge is reached. while ramping, the buck is forced into pwm 2 r/w vb_mem_go 0: hold vbuckmem at current setting. 1: ramp buckmem to configured voltage. while the voltage is ramping, write access is blocked to buckmem register. vbuckmem_go is cleared when the target voltage is reached. while ramping, the buck is forced into pwm 3 r/w vldo2_go 0: hold ldo2 at current setting. 1: ramp ldo2 to configured voltage. while the voltage is ramping, write access is blocked to ldo2 register. vldo2_go is cleared when the target voltage is reached (ignored if ldo2_conf was asserted) 4 r/w vldo3_go 0: hold vldo3 at current setting. 1: ramp vldo3 to configured voltage. while the
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 126 of 183 ? 2016 dialog semiconductor register a d dress bit t ype label description voltage is ramping, write access is blocked to ldo3 register. vldo3_go is cleared when the target voltage is reached (ignored if ldo3_conf was asserted) 5 r/w vperi_sw_en 0: disconnects vperi_sw pin from buck 1: vperi_sw closed (controllable from sequencer) 6 r/w vmem_sw_en 0: disconnects vmem_sw pin from buck 1: vmem_sw closed (controllable from sequencer) 7 r/w v_lock 0: allows writing new values into buck and ldo voltage registers 1: disables voltage re - programming from the host (enable/disable, dvc ramping, power sequencing including deferred update still possible) register a d dress bit t ype label description r61 pulldown 0 r/w core_pd_dis 0: enable pull down resistor 1: no pull down resistor in disabled mode 1 r/w pro_pd_dis 0: enable pull down resistor 1: no pull down resistor in disabled mode 2 r/w mem_pd_dis 0: enable pull down resistor 1: no pull down resistor in disabled mode 3 r/w ldo1_pd_dis 0: enable pull down resistor 1: no pull down resistor in disabled mode 4 r/w ldo2_pd_dis 0: enable pull down resistor 1: no pull down resistor in disabled mode 5 r/w ldo5_pd_dis 0: enable pull down resistor 1: no pull down resistor in disabled mode 7:6 r/w reserved
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 127 of 183 ? 2016 dialog semiconductor 17 programmable b attery c harger the system power and charger control block contains the following functions: automatic selection of the system power source (vddout) from either the wall charger dcin, vbus or vbat with preference given to dcin. an active diode function allows seamless switching of the power source. the optional external active diode controller pro vides an extended current power path from the battery. the 3 - way power path switch supports the automatic power selection from up to two connected external chargers (wall charger/usb charger). battery disconnection switch to allow instant - on system start - u p with discharged main battery . independent vbat tracking mode buck regulator supplying system power out of vbus with an efficiency > 85 % @ 1000 ma load current . individual programmable current limits for the usb and dcin supply input . automatic usb batte ry charging specification rev.1.0 compliant charger type detection, usb suspend mode support . an autonomous battery charger with pre - configurable current limits and programmable eoc voltages (3.65 v to 4.425 v ), current monitoring (always active when the c harger is on) and otp programmable eoc currents. protection against continuous top charging extends battery life (configurable re - charge hysteresis) . integrated control over battery pre - charge (including battery pack wake - up), constant - current and constant - voltage charging phases with die temperature thermal feedback (automatic adjustment to maximum charge rate without overheating) . dynamic charger current control (dccc), providing system power and charging the battery without exceeding the supply current l imits . battery temperature qualified charging (using gp - adc) with default settings loaded from otp . battery charging termination by current (using gp - adc) with default setting loaded from otp . charge current thermal regulation by ic temperature (using gp - a dc) . programmable charge termination by timer for safety . 17.1 high e fficiency c harger dc - dc b uck c onverter in order to minimize the total system power loss at high input currents, da9053s main system power v ddout is supplied out of a high efficient dcdc conve rter, which is able to track v bat +250 mv (with minimum v ddout = 3.75 v ). when powering up v ddout the dc - dc converter provides a soft - start circuitry and the current limit is implemented to meet the usb 2.0 specification for currents spikes where charge peaks are always less than an equivalent bypass capacitive load of 10 f. an integrated over voltag e protection and supply selection controls the behaviour of these power paths. the buck converter operates at a high frequency (2 mhz). this switching frequency is chosen to be high enough to allow the use of a small 2.2 h or 4.7 h inductor. to guarantee high efficiency at high load currents the serial resistance of the coil is limited to 100 m ? (at 1000 ma). under light load conditions the buck converter can be forced by the host to a low current pfm mode. 17.2 charger s upply d etection/vbus m onitoring da9053 provides a dual mode charger input vbus, which can be supplied either from a usb host/hub, a usb type host/hub charger or a dedicated wall charger. to protect da9053 against destruction from invalid supplies an over voltage protection circuitry will discon nect every charger that supplies more than 5.6 v .
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 128 of 183 ? 2016 dialog semiconductor at the vbus input a connected usb 2.0 compliant host/hub will supply 5 v and is able to provide maximum 100 ma whenever it is operational. a dedicated wall charger or usb host/hub charger has to be differe ntiated from a usb host/hub because it usually provides charging currents greater 100 ma. da9053 has therefore a built - in circuitry to detect the attached charger type at vbus. for a dedicated charger da9053 has to detect a short between d+ and d - (with a maximum resistance of 200 ?). from then on the usb charger specification allows the connected charger to charge the device with a current up to 1500 ma. if alternatively the voltage on d - was detected to be less than v dat_ref (0.25 v to 0.4 v ) da9053 will keep the current limit at 100 ma. in addition to the combined charger input vbus da9053 provides a second charger input dcin that allows a wall charger to be connected in parallel. this supply will receive priority as soon as it is detected. vcenter will then be connected to dcin. note the configured default maximum current values have to allow the application being powered completely from the external supply (in the case of a deep discharged battery) but at the same time have to secure that all potential chargers are able to provide the automatically selected maximum average current. 17.3 vbus o ver - v oltage p rotection and usb s uspend da9053 includes an over - voltage protection circuit that disconnects vbus or dcin from the vbus_prot and dcin_prot inputs via the external p - fets whenever the vbus or dcin voltage is above the threshold. if both inputs are connected to valid supplies dcin will receive priority and vbus will be disconnected via the p - fet. this circuit also supports a usb suspe nd mode where the vbus_prot path is switched off (disabling the usb charger path) and the vdd_out main supply is switched to the battery. additionally, da9053 support s a bus powered low - power mode. in this mode the charger buck is forced to a pfm mode ( s le ep mode) to ensure the system is backed up with minimum power dissipation when being supplied from an external supply. monitoring of the vbus and dcin voltage is always provided, allowing the host processor to detect a removal of the vbus also in suspend m ode. the removal of supplies will issue interrupt requests and trigger a wake - up in power - down mode if is still present after a debounce time of 10 ms. 17.4 battery p re - c harge m ode battery pre - charge mode is started and controlled automatically by da9053. this is needed to ensure that a completely empty battery can be charged without the intervention of the host processor. in the event of a heavily discharged battery the battery is disconnected from the v ddout supply so that the system may be started. the charge r then powers the v ddout rail from one of the supply paths as described above, allowing the ldos and buck converter to be switched on. pre - charge mode is started when a charger has been detected and v ddout is greater than v bat + 200 mv (or > 3.6 v ). the pr e - charge mode also handles the re - enable of a battery pack which has had an internal safety switch activated (from deep discharge). the safety switch will be reset by applying a current through the diode in the safety switch, charging the battery cell up t o about 2.8 v where the switch will be closed again. da9053 can optionally drive a flashing led at gpio 10 or 11 that will indicate the invisible battery charging until the application is able to power up.
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 129 of 183 ? 2016 dialog semiconductor 17.5 fast l inear - c harge m ode battery linear - charge mode is initiated automatically once the battery voltage has exceeded the bat_fault threshold for a minimum of 40 ms (to allow a battery safety switch to close) the linear charge mode has two phases of operation: 1. constant current (cc) mode. 2. constant voltage (cv) mode. if the battery voltage (v bat ) is less than the target voltage, the charging starts in cc mode. temperature supervision of the battery by the gp - adc channel 2 is started and charging is only allowed if the battery temperature i s in the correct range. if a tbat fault condition is detected while charging the battery, charging will be suspend until the battery temperature is back in the correct range, except in the case that the charging end point has been reached. the cc mode has 64 possible current settings ranging from 30 ma to 1890 ma, controllable by the host processor via the power manager bus. when the battery voltage approaches the target regulation voltage level the charger control loop changes over to cv mode. note that th e cc and cv mode actually operate in parallel, with the cc loop limiting the charging current and the cv loop limiting the charging voltage. the charging current will be measured automatically by the gp - adc, generating an averag e current reading over 10 s period that will be used to determine the charging end point detection. this allows for flexibility in determining when to automatically stop charging for different sizes and types of battery. 17.6 thermal c harge c urrent c ontrol during charging the temperature of da9053 (tjunc) is continuously supervised by the gp - adc against overheating. a thermal supervision circuit reduces the charge current via a current/temperature control whenever the die temperature attempts to rise above a preset value of tchargelow (90 c). it completely suspends charging when tchargesuspend (120 c) has been reached. this protects da9053 from excessive temperature but allows the application to push the limits of the power handling capability of a given circuit board without risk of dama ge. another benefit of the thermal limit is that the charge current can be set according to typical, not worst - case, ambient temperatures for a given application with the assurance that the charger will automatically reduce the current in worst - case condit ions. whenever the package temperature (tjunc, see chapter gp - adc) crosses a threshold from the table below the thermal control will raise the (internal) temperature class and reduce the battery charge current limit towards the related value. it will incr ease the charge current limit only if the temperature drops below the threshold of the actual class 1. this prohibits a continuous change of the charging current around a temperature threshold. the thermal charge current control can be disabled but this wi ll increase the risk for a complete thermal shutdown from the internal temperature supervision inside high - power applications. table 51 : thermal c harge c urrent c ontrol tjunc ( c) class charge current l imit (ma) ichg_bat (register v alue) <90 0 1890 111111 >90 1 1650 110111 >95 2 1350 101101 >100 3 1050 100011 >105 4 750 011001
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 130 of 183 ? 2016 dialog semiconductor >110 5 450 001111 >115 6 charging suspended 000000 17.7 dynamic c harging c urrent c ontrol (dccc) and a ctive - d iode if the combination of the system load plus the battery charging current (pre - charge or fast linear charging) exceeds the charger buck output current (which is limited by the current limitation of the buck) into the vddout node, then the output voltage on vddout will start to drop down to vbat (whic h automatically reduces the charging current). when the vddout voltage drops to 3.6 v , and the charger buck is still in current limit, the charging current to the battery will be reduced until it reaches zero or the buck runs below its current limit. once the vddout is above >3.75 v or the buck runs below its current limit, the charging will be increased until it reaches the programmed setting. the battery charging control includes an active - diode circuit that will automatically provide current to the syst em if the vddout voltage falls below the vbat voltage. if large currents or very low resistance in series with the battery output is required the path can be extended by an external power fet using the external active - diode controller. figure 48 : dccc and a ctive diode o peration 17.8 programmable c harge t ermination by t ime the battery charger block will provide a safety timer controlling the maximum time allowed for battery charging. the charge timer is programmable through the power ma nager bus. the total charge time is defined as the time from when the battery charging was enabled (both for fast and pre - charge mode charging). during fast charge mode the time is dynamically extended whenever the current into the battery is automatically reduced from dccc or thermal regulation towards less than for example, 50% of the configured maximum charge current. this change in charge time is inversely proportional to the change in charge current. the dynamic safety timer is limited to eight times t he programmed clock period and can alternatively be configured towards a fixed timer. if the timer expires (reaches zero) an interrupt request is issued and charging is disabled. 17.9 backup b attery c harger / b attery s witch the backup battery charger provides a constant charge current with a programmable top off charging voltage for charging of lithium - manganese coin cell batteries and super capacitors. charging current 1 0 0 0 2 0 0 3 0 0 4 0 0 i o u t i v b u s 5 0 0 6 0 0 i c h g _ b a t 0 1 0 0 2 0 0 3 0 0 4 0 0 5 0 0 i o u t [ m a ] c u r r e n t [ m a ] 6 0 0 e x a m p l e o f d c c c & a c t i v e d i o d e o p e r a t i o n i n u s b h i g h p o w e r m o d e e x t r a c u r r e n t s u p p l i e d b y a c t i v e d i o d e
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 13 1 of 183 ? 2016 dialog semiconductor is programmable from 100 a to 1000 a (in steps of 100 a) and from 1 ma to 6 ma (in steps of 1 ma). termination voltage is programmable in 100 mv steps from 1.1 v to 3.1 v . charging is suspended whenever the termination voltage has been reached and the charging current drops below 50 a. charging is re - enabled whenever the backup battery voltag e drops 0.2 v below the target termination voltage. it switches off automatically during no - power mode (npor asserted). the function of the battery switch is to provide power to vdd_ref (ldocore) from the appropriate battery or supply, depending on condit ions as described below. if only the backup battery is applied, the switch will automatically connect vdd_ref to this battery. if the power path provides a voltage from the main battery or an external supply that is higher than vbbat the switch will autom atically connect to vddout. during no - power mode vdd_ref will always be disconnected from the backup battery to prohibit a discharge in advance to the initial start - up of the application. if the target voltage of the backup battery is configured lower than vddcore the automatic connection of vbbat to vdd_ref is disabled. as the main battery is discharged the system will be warned via the vddout voltage supervision with an interrupt. if no action is taken to restore the charge on the main battery and discha rging is continued the battery switch will disconnect the input of the ldocore ( vdd_ref ) from the main battery and connect to the backup battery when vddout < vbbat - 0.2 v . if the application includes no backup battery or the backup battery voltage is co nfigured to be less than ldocore (intended to provide only a low voltage rtc supply to the host) the automatic switch to the backup battery can be disabled. having a typical 3 v backup battery the main battery voltage at which is switched over from main to backup battery is 2.8 v . there is a hysteresis in this switch operation so vdd_ref will not be reconnected to main battery until the main battery voltage is greater than vbbat (3.0 v ) typically. the backup battery charger includes a reverse current protection against vdd_ref and can also be used as an ultra - low quiescent always on supply for low voltage/power rails (on during reset mode ). 17.10 battery c harger table 52 : chargin g control r egisters register a d dress bit t ype label description r62 chg_buck 3:0 r/w iset_buck 0000: 80 ma 0001: 90 ma 0010: 100 ma 0011: 110 ma 0100: 120 ma 0101: 400 ma 0110: 450 ma 0111: 500 ma 1000: 550 ma 1001: 600 ma 1010: 800 ma 1011: 1000 ma 1100: 1200 ma 1101: 1400 ma 1110: 1600 ma 1111: 1800 ma 4 r/w chg_buck_en this bit is controlled by the charger state machine. if reset by the host only a charger removal and re - attach starts automatic charger control again. if set to 1 the
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 132 of 183 ? 2016 dialog semiconductor automatic charger control is started immediately. 5 r/w chg_buck_lp when set to 1 the charger buck is forced to the pfm (sleep) mode and charging will be suspended. automatically cleared when starting charging/re - charging 6 r/w chg_usb_ilim 0: no automatic usb charger type detection (always use iset_usb) 1: automatic usb supply current limit enabled (d+,d - sensing, start with iset_buck) 7 r/w chg_temp 0: thermal charging control disabled 1: thermal charging control enabled register a d dress bit type label description r63 wait_cont 3:0 r/w delay_time 0000: 0 s 0001: 540 s 0010: 1.0 m s 0011: 2.0 m s 0100: 4.1 m s 0101: 8.2 m s 0110: 16.4 m s 0111: 32.8 m s 1000: 65.5 m s 1001: 131 m s 1010: 262 m s 1011: 524 m s 1100: 1.0 s 1101: 2.1 s 1110: 4.2 s 1111: reserved 4 r/w en_32kout 0: 32k clock buffer off 1: 32k clock buffer on 5 r/w wait_mode 0: wait for gpio10 to be active 1: delay timer mode (start timer and wait for expire) 6 r/w rtc_clock 0: no gating of rtc calendar clock 1: clock to rtc counter is gated until wait is asserted 7 r/w wait_dir 0: wait during power - up sequence 1: wait during power - up and power - down sequence register a d dress bit t ype label description r64 iset 3:0 r/w iset_usb 0000: 80 ma 0001: 90 ma 0010: 100 ma 0011: 110 ma
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 133 of 183 ? 2016 dialog semiconductor 0100: 120 ma 0101: 400 ma 0110: 450 ma 0111: 500 ma 1000: 550 ma 1001: 600 ma 1010: 800 ma 1011: 1000 ma 1100: 1200 ma 1101: 1400 ma 1110: 1600 ma 1111: 1800 ma 7:4 r/w iset_dcin 0000: 80 ma 0001: 90 ma 0010: 100 ma 0011: 110 ma 0100: 120 ma 0101: 400 ma 0110: 450 ma 0111: 500 ma 1000: 550 ma 1001: 600 ma 1010: 800 ma 1011: 1000 ma 1100: 1200 ma 1101: 1400 ma 1110: 1600 ma 1111: 1800 ma register a d dress bit t ype label description r65 bat_chg 5:0 r/w ichg_bat note 1 battery charger current limit (cc) 000000: 0 ma (charging suspended) 000001: 30 ma 000010: 60 ma 000011: 90 ma 000100: 120 ma 000101: 150 ma 000110: 180 ma 000111: 210 ma 001000: 240 ma 001001: 270 ma 001010: 300 ma 001011: 330 ma ... 110111: 1650 ma 111000: 1680 ma 111001: 1710 ma
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 134 of 183 ? 2016 dialog semiconductor 111010: 1740 ma 111011: 1770 ma 111100: 1800 ma 111101: 1830 ma 111110: 1860 ma 111111: 1890 ma 7:6 r/w ichg_pre battery pre - charge current limit 00: 0 ma (charging suspended) 01: 20 ma 10: 40 ma 11: 60 ma note 1 3 - bit trimming are used to adjust the absolute value via otp . register a d dress bit t ype label description r66 chg_cont 2:0 r/w vch_thr charger buck reduces the actual current limit if external supply voltage drops below: 000: 3.8 v 001: 4.0 v 010: 4.1 v 011: 4.2 v 100: 4.3 v 101: 4.4 v 110: 4.5 v 111: 4.8 v 7:3 r/w vchg_bat battery charger voltage limit (cv) 00000: 3.650 v 00001: 3.675 v 00010: 3.700 v 00011: 3.725 v 00100: 3.750 v 00101: 3.775 v 00110: 3.800 v 00111: 3.825 v 01000: 3.850 v 01001: 3.875 v 01010: 3.900 v 01011: 3.925 v 01100: 3.950 v 01101: 3.975 v 01110: 4.000 v 01111: 4.025 v 10000: 4.050 v 10001: 4.075 v 10010: 4.100 v (li - polymer) 10011: 4.125 v 10100: 4.150 v
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 135 of 183 ? 2016 dialog semiconductor 10101: 4.175 v 10110: 4.200 v (li - ion) 10111: 4.225 v 11000: 4.250 v 11001: 4.275 v 11010: 4.300 v 11011: 4.3250 v 11100: 4.350 v 11101: 4.375 v 11110: 4.400 v 11111: 4.425 v register a d dress bit t ype label description r67 input_cont 3:0 r/w tctr note 1 0000: charge time out disabled 0001: 30 mins remaining 0010: 60 mins remaining 0011: 90 mins remaining 1010: 300 mins remaining ... 1111: 450 mins remaining 4 r/w vbus_susp when set to 1, the usb charger path is set into suspend mode, where the power path from vbus_prot to vcenter is switched off. automatically cleared when usb supply is removed 5 r/w dcin_susp when set to 1, the dcin charger path is set into disconnect mode, where the power path from dcin_prot to vcenter is switched off. automatically cleared when dcin supply is removed 6 r/w vchg_drop charger re - enabled if vbat drops below vchg_bat minus 0: 100 mv 1: 200 mv 7 r/w tctr_mode 0: total charge time is extended during periods with reduced charge current 1: total charge time is fixed note 1 changing the value of tctr sets the timer to the new value. the timer is paused whenever the ichg_bat=0ma. the current timer value can be read from the chg_time register. the timer counts down from the loaded value. register a d dress bit t ype label description r68 chg_time 7:0 r chg_time remaining minutes until charging time out 00000000: charging ended 00000001: 2 mins remaining 00000010: 4 mins remaining
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 136 of 183 ? 2016 dialog semiconductor ... 11111111: 510 mins remaining 17.11 backup battery c harger table 53 : backup b attery c harging c ontrol r egisters register a d dress bit t ype label description r69 bbat_cont 3:0 r/w bcharger_vset 0000: disabled 0001: 1.1 v 0010: 1.2 v 0011: 1.4 v 0100: 1.6 v 0101: 1.8 v 0110: 2.0 v 0111: 2.2 v 1000: 2.4 v 1001: 2.5 v 1010: 2.6 v 1011: 2.7 v 1100: 2.8 v 1101: 2.9 v 1110: 3.0 v 1111: 3.1 v 7:4 r/w bcharger_iset 0000: disabled 0001: 100 a 0010: 200 a 0011: 300 a 0100: 400 a 0101: 500 a 0110: 600 a 0111: 700 a 1000: 800 a 1001: 900 a 1010: 1 ma 1011: 2 ma 1100: 3 ma 1101: 4 ma 1110: 5 ma 1111: 6 ma
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 137 of 183 ? 2016 dialog semiconductor 17.12 white led d river and b oost c onverter da9053 will provide the capability for supplying the power for at least 5 white leds in series. using the components described in this datasheet to drive three independent strings of 5 leds the inductive boost converter will provide around 24 v at a forward current of max.78m a. (to handle strings of greater than 5 leds higher voltages are also possible also by using lower voltages to driving fewer than 5 leds more than 50 ma will be possible by choosing different external components, please contact your dialog representative f or specific cases). the regulation scheme will ensure that the correct voltage is generated for the series connected leds. this is achieved by controlling the output voltage of the boost converter such that the lowest voltage at the control loop enabled pi ns led1_in / led2_in / led3_in exceeds a threshold voltage of approx. 0.7 v at the programmed current. the over voltage protection will protect the block from a disconnected load, limiting the output voltage of the boost converter. the over voltage protect ion threshold is defined by an external voltage divider compared with a reference voltage of 1.41 v . whenever over voltage is detected or the current through the inductor gets larger than the maximum configured limit, the boost switches off. figure 49 : example of w hite led b acklight a pplication each white led output driver will have a programmable logarithmic idac with 256 steps to set the output current. the dynamic range is 50 a to 26 ma resulting towards a step multiplicati on of the 255th root of 520. all three drivers will have individual controls to enable a led current ramping with 1ms per step. the relative matching of identical configured idacs is designed to be within the range of +/ - 3.25% at full current. note all ledx_in ports that are connected (via led) to a voltage rail potentially >5.5 v have to be enabled at a current level that protects the port against high voltages. if a current drive input is not connected to the boost, its regulation has to be disabled in the control register allowing an enabled boost to stop increasing at the intended voltage level. disabling the current sink without disabling it for the boost control will potentially damage the current drive. it is mandatory to prohibit voltages higher t han 5.5 v at the current sink inputs. a balanced configuration is recommended with a similar type and number of leds and a similar current for the connected led strings. always enable all connected current sinks before enabling the boost. the current sink s offer a pwm control. the generated pwm signal is of duty cycle from 16 to 100%, with a repetition frequency of 21 khz and 95 steps (using 2 mhz clock for each step). a pwm ratio greater than 95 results in the output switch being permanently closed. durin g the duty cycle the current sinks use the individual configured current setting. the low level current of the pwm led 50 ma boost converter sw_boost leds 2uf control current drive 1 led1_in 4.7u h vdd out r shunt 0.1ohm boost_sensep boost_prot ntljf4156n r fb1 1mohm typ r fb2 75 kohm typ current drive 2 led2_in boost_sensen current d rive 3 disconnected drive has to be disabled in the boost control register!
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 138 of 183 ? 2016 dialog semiconductor controlled led strings is common. the pwm control can also be made to dim between its actual value and a new value at a rate of 40ms per step . when set to zero the pwm ratio will change immediately. note it is strongly recommended that pwm controlled led strings, which are enabled for the boost control loop are configured balanced with identical pwm duty cycle and high level current settings. if boost driven strings contain more than 4 leds small current deltas or a current ramping are highly recommended because an immediate switch to very low currents can already generate critical input voltages at the current sinks. led3 includes a pwm - only mode (no current control) which automatically disables the led3 input towards the boost control with a duty cycle from 0 to 100%. in conjunction with the gpio 14 and 15 this offers a common anode tricolour leds brightness control. this mode is intended to drive a single led from supply voltages below 5.5 v and requires an appropriate serial resistor. note the efficiency of the boost converter is dominated by the external losses. to achieve a good efficiency, the coil, diode and transistor losses should be minimized. 2 mhz mode will achieve lowest current ripple but especially for low output currents 1 mhz will provide better efficiency. 17.13 boost an d led d river table 54 : boost and led driver control r egisters register a d dress bit t ype label description r70 boost 0 r/w boost_en 0: boost converter disabled 1: boost converter enabled 1 r/w led1_in_en 0: led1 input is disabled for boost voltage control (mandatory, if not connected to boost) 1: led1 is included for lowest input voltage 2 r/w led2_in_en 0: led2 input is disabled for boost voltage control (mandatory, if not connected to boost) 1: led2 is included or lowest input voltage 3 r/w led3_in_en 0: led3 input is disabled for boost voltage control (mandatory, if not connected to boost) 1: led3 is included for lowest input voltage 4 r/w boost_ilim 0: 710 ma boost current limitation 1: 1000 ma boost current limitation 5 r/w boost_frq 0: 1 mhz boost switching frequency 1: 2 mhz boost switching frequency 6 r/w m_b_fault mask boost failure caused nirq 7 r e_b_fault if set boost the over voltage or over current limitation triggered an error event
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 139 of 183 ? 2016 dialog semiconductor register a d dress bit t ype label description r71 led_cont 0 r/w led1_en 0: led1 current sink disabled, led1_in_en is automatically set to zero 1: led1 current sink enabled 1 r/w led1_ramp 0: no led1 current ramping 1: new target led1 current will be adjusted by ramping (1 step/1ms) 2 r/w led2_en 0: led2 current sink disabled, led2_in_en is automatically set to zero 1: led2 current sink enabled 3 r/w led2_ramp 0: no led2 current ramping 1: new target led2 current will be adjusted by ramping (1 step/1ms) 4 r/w led3_en 0: led3 current sink disabled, led3_in_en is automatically set to zero 1: led3 current sink enabled 5 r/w led3_ramp 0: no led3 current ramping 1: new target led3 current will be adjusted by ramping (1 step/1ms) 6 r/w led3_icont 0: led3 is pwm - only controlled (gpio14/15 mode), ledmin_current and led3_current are not used, led3_en and led3_in_en are automatically set to zero 1: led3 is current controlled (led1/2 mode) 7 r/w sel_led_mode 0: reserved 1: the boost is in current driving mode register a d dress bit t ype label description r72 ledmin_123 7:0 r/w ledmin_current led1/2/3 current value during pwm idle time: 00000000: 50.0 a 00000001: 51.2 a (+0.213 db) 00000010: 52.5 a (+0.213 db) ... 11111111: 26000 a register a d dress bit t ype label description r73 led1_conf 7:0 r/w led1_current led1 current value: 00000000: 50.0 a 00000001: 51.2 a (+0.213 db) 00000010: 52.5 a (+0.213 db) ... 11111111: 26000 a
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 140 of 183 ? 2016 dialog semiconductor register a d dress bit t ype label description r74 led2_conf 7:0 r/w led2_current led2 current value: 00000000: 50.0 a 00000001: 51.2 a (+0.213 db) 00000010: 52.5 a (+0.213 db) ... 11111111: 26000 a register a d dress bit t ype label description r75 led3_conf 7:0 r/w led3_current led3 current value: 00000000: 50.0 a 00000001: 51.2 a (+0.212 db) 0000010: 52.5 a (+0.212 db) ... 11111111: 26000 a register a d dress bit t ype label description r76 led1_cont 6:0 r/w led1_pwm led1 intensity control in periods of 2 mhz clock (period 21 khz = 95 cycles) 0000000: off 0000001: 1 % (not used) .... 0001111: 15 % (not used) 0010000: 16 % .... 1011111: 100 % >1011111: 100 % led1_current is used during the duty cycle. during idle times the alternate current is taken from ledmin_current. 7 r/w led1_dim 0: led1 pwm ratio changes instantly 1: led1 ramps between changes in pwm ratio with 40 ms per step register a d dress bit t ype label description r77 led2_cont 6:0 r/w led2_pwm led2 intensity control in periods of 2 mhz clock (period 21 khz = 95 cycles) 0000000: off 0000001: 1 % (not used) .... 0001111: 15 % (not used) 0010000: 16 %
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 141 of 183 ? 2016 dialog semiconductor .... 1011111: 100 % >1011111: 100 % led2_current is used during the duty cycle. during idle times the alternate current is taken from ledmin_current. 7 r/w led2_dim 0: led2 pwm ratio changes instantly 1: led2 ramps between changes in pwm ratio with 40 ms per step register a d dress bit t ype label description r78 led3_cont 6:0 r/w led3_pwm led3 intensity control in periods of 2 mhz clock (period 21 khz = 95 cycles) 0000000: off 0000001: 1 % (not used if current controlled) .... 0001111: 15 % (not used if current controlled) 0010000: 16 % .... 1011111: 100 % >1011111: 100 % led3_current is used during the duty cycle. during idle times the alternate current is taken from ledmin_current (led1/2 mode). if led3_icont is not asserted the current control with be disabled and the output will be just switched on and off (gpio14/15 mode). 7 r/w led3_dim 0: led3 pwm ratio changes instantly 1: led3 ramps between changes in pwm ratio with 40ms per step register a d dress bit t ype label description r79 led4_cont 6:0 r/w led4_pwm gpio14 led on - time (low level at gpio 14, period 21 khz = 95 cycles of 0.5 s) 0000000: off 0000001: 1 % 0000010: 2 % (1 s bursts) 0000011: 3 % 0000100: 4 % 0000101: 5 % 0000110: 6 % 0000111: 7 % 0001000: 8 % 0001001: 9 % 0001010: 10 %
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 142 of 183 ? 2016 dialog semiconductor 0001011: 11 % 0001100: 12 % 0001101: 13 % 0001110: 14 % 0001111: 15 % 0010000: 16 % .... 1011111: 100 % >1011111: 100 % 7 r/w led4_dim 0: led4 pwm ratio changes instantly 1: led4 ramps between changes in pwm ratio with 40 ms per step register a d dress bit t ype label description r80 led5_cont 6:0 r/w led5_pwm gpio15 led on - time (low level at gpio 15, period 21 khz = 95 cycles of 0.5 s) ) 0000000: off 0000001: 1 % 0000010: 2 % (1 s bursts) 0000011: 3 % 0000100: 4 % 0000101: 5 % 0000110: 6 % 0000111: 7 % 0001000: 8 % 0001001: 9 % 0001010: 10 % 0001011: 11 % 0001100: 12 % 0001101: 13 % 0001110: 14 % 0001111: 15 % 0010000: 16 % .... 1011111: 100 % >1011111: 100 % 7 r/w led5_dim 0: led5 pwm ratio changes instantly 1: led5 ramps between changes in pwm ratio with 40 ms per step
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 143 of 183 ? 2016 dialog semiconductor 18 monitoring adc and t ouch s creen i nterface 18.1 adc o verview the da9053 provides an analog to digital converter (adc) with 10 - bits resolution and track and hold circuitry combined with an analog input multiplexer. the analog input multiplexer will allow conversion of up to 10 different inputs. the track and hold circuit ensures stable input voltages at the input of the adc during the conversion. the adc is used to measure the following inputs: channel 0: vddout C measurement of the system voltage channel 1: ich C internal battery charger current measurement channel 2: tbat C output from the battery ntc channel 3: vbat C measurement of the battery voltage channel 4: adc_in4 C high impedance input (0 v to 2.5 v ) channel 5: adc_in5 C h igh impedance input (0 v to 2.5 v ) channel 6: adc_in6 C high impedance input (input divider, 0 v to 2.5 v ) channel 7: xy C tsi interface to measure the x and y voltage of the touch screen resistive potentiometers channel 8: internal tjunc. - sense (internal temp. sensor) channel 9: vbbat C measurement of the backup battery voltage figure 50 : adc b lock d iagram 18.2 input mux the mux selects from and isolates the 10 inputs and presents the channel to be measured to the adc input. when selected, an input amplifier on the vddout (and vbat) channel subtracts the vddcore reference voltage and scales the signal to the correct value for the adc. 18.3 adc the adc uses a sample and hold successive approximation switched capacitor architecture. it is supplied from internal core supply rail vddcore (2.5 v ). it can be used either i n high speed mode with measurements sequences repeated every 1ms or in economy mode with sequences performed every 10ms . mux track and hold adc 2 . 5 v vref power manager r egisters adcin 4 - adcin 6 tbat connections from charger vddout ich tbat vbat adcin 6 tsi
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 144 of 183 ? 2016 dialog semiconductor 18.4 manual c onversion m ode for manual measurements the adc powers up, one conversion is done on the specified channel and the 10 - bit result is stored. after the conversion is completed, the adc powers down again and an irq event flag is set (end of manual conversion). the generation of this irq can be masked by t he irq mask. note: the irq must be cleared before subsequent manual measurements can be made. 18.5 automatic m easurements s cheduler the automatic measurement scheduler allows monitoring of the system voltage vddout, the charging current ich, the battery temperat ure tbat and the touch screen interface xy. additionally, the auxiliary channels adcin4 - 6 are able to be automatically monitored with upper and low thresholds set by power manager registers to give a nirq event if a measurement is outside these levels. all measurements are handled by the scheduler system detailed below. the scheduler performs a sequence of 10 slots continually repeated according to the configured mode. if the tsi is enabled the first half slot performs either an automatic or a manual conver sion. the second half slot performs tsi actions and measurements. if the tsi measurement is disabled there is no split of the slot and only the first conversion is performed. a slot requires 100s. the pattern of measurements over the 10 slots depends upon the charging mode. automatic measurements of vddout, ich and tbat are made during charging. these cease when not charging. when automatic measurements are disabled, the manual measurements are made immediately and unused automatic measurements will handle manual conversion requests. the action of each automatic measurement follows. beside the tsi automatic measurements only store the 8msbs of the adc measurement. figure 51 : example s equence of auto - adc m easurements 18.6 a0: vddout l o w v oltage nirq m easurement m ode vddout is measured and compared with a threshold. if the reading is below this level for a number of three consecutive readings an error event is generated. if nirq was asserted the automatic measurement of channel vddout is paused until the host has cleared the associated event flag (the event causing value is kept inside the result register). if no action is taken to restore the vddout voltage (discharging the battery is continued) the host may consider to switch off option al 1 2 3 4 0 s l o t n o a 0 x a 1 m a 4 a 2 e x a m p l e s e q u e n c e o f a u t o - a d c m e a s u r e m e n t s t s i , n o c h a r g i n g , t s i _ d e l a y < = 1 , t s i _ s k i p = 0 a 0 x m m a 4 m t s i , w i t h c h a r g i n g t s i _ d e l a y < = 1 , t s i _ s k i p = 2 s l o t s e a c h s l o t a l l o w s 1 a u t o m a t i c o r m a n u a l m e a s u r e m e n t a n d 1 t s i m e a s u r e m e n t t o b e m a d e a 0 - a u t o m a t i c m e a s u r e m e n t o f v d d o u t ( m u x c h a n n e l 0 ) a 1 - a u t o m a t i c m e a s u r e m e n t o f i c h ( m u x c h a n n e l 1 ) a 2 - a u t o m a t i c m e a s u r e m e n t o f t b a t ( m u x c h a n n e l 2 ) a 4 - a u t o m a t i c m e a s u r e m e n t o f a d c i n 4 ( m u x c h a n n e l 4 ) a 5 - a u t o m a t i c m e a s u r e m e n t o f a d c i n 5 ( m u x c h a n n e l 5 ) a 6 - a u t o m a t i c m e a s u r e m e n t o f a d c i n 6 ( m u x c h a n n e l 6 ) a 8 - a u t o m a t i c m e a s u r e m e n t o f t j u n c w i t h g a i n 3 ( m u x c h a n n e l 8 ) t s i - a u t o m a t i c x & y ( & z ) m e a s u r e m e n t f o l l o w e d b y a p e n d e t e c t i o n ( m u x c h a n n e l 7 ) m i n d i c a t e s t i m e s l o t s w h e n a m a n u a l m e a s u r e m e n t c a n b e m a d e y y z z p p - x a 0 a 1 m a 4 a 2 n o t s i , n o c h a r g i n g a 0 m m a 4 m n o t s i , w i t h c h a r g i n g 5 6 7 m a 5 a 6 m a 5 m m a 5 a 6 m a 5 m - y x p y x 8 9 m a 8 m a 6 m a 8 m a 6 p y - p
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 145 of 183 ? 2016 dialog semiconductor always on blocks (backup battery charger or supplies, that are not disabled when powering down to reset mode) to save energy later on. the multiple reading provides a debouncing of the vddout voltage before issuing a nirq. the assertion of nirq can be masked by irq mask. 18.7 a1: ich (and ich_bat a verage) m easurement m ode when the battery is being charged in fast charge mode the ich current is measured automatically every 1 ms or 10 ms and an average value is determined by adding the result to an 18 - bit accumulator and latching the top eight bits every 1024 samples (during high speed mode nine measurements are ignored before performing an update). this provides an average charging current value every 10.24 s. when the ich_bat falls below the value set (and the other requirements for charging end detect are met), an irq will be flagged. the irq can be masked. 18.8 a2: tbat and b attery t emperature w arning nirq m easurement m ode when the battery is being charged, the tbat voltage is measured automatically. duri ng this measurement, a 50 a current is sourced to the battery temperature sense resistor from the tbat pin. during production testing, the tbat high and low thresholds are programmed into the otp memory, with adjustments made to correct for the accuracy o f the 50 a current source and the high and low temperature resistance of the ntc resistor etc. the measurement result is used to protect the battery pack from damage during charging at too high temperatures. temperature is flagged by three threshold level s held in the threshold registers (loaded from otp at start - up). if three consecutive readings of tbat are outside the configured range, then charging is disabled, an event flag is set and an interrupt is generated. the processor can then either service th e irq and turn off charging or do nothing. if nothing is done, the fast charge block will start charging again as soon as the temperature readings are inside the programmed range. the generation of this irq can be masked. 18.9 a4, a5, a6: automatic m easurement and high/low t hreshold w arning nirq m ode the automatic measurement result of channel adc_in4 is stored. if a reading of a4 outside the programmed range then an event flag is set. if nirq was asserted the automatic measurement of channel adc_in4 is paused u ntil the host has cleared the associated event flag (the event causing value is kept inside the result register). if debouncing is selected the event will only be asserted if two consecutive measurements override the same threshold. the assertion of nirq c an be masked by irq mask. the same functionality is available at adc_in5 and adc_in6. in addition it is possible to use adcin_4 with a 15 a current source that allows automatic measurement of a resistor value. during automatic measurements the enabled cur rent source is dynamically switched - off at the end of the conversion and switched - on one slot prior to the next adcin_4 measurement (to enable minimum current consumption, but external capacitance to settle) ; otherwise its status is static. 18.10 a8: automatic m easurement of i nternal t emperature selection of channel 8 (tjunc) will be used to measure the output of the internal temperature sensor generated out of a ptat current from the bgr. the channel 8 measures the output of the temperature sensor with a gain of 3. an offset register can be used for a one point calibration of the temperature sensor. 18.11 a3, a9: manual m easurement vbat and vbbat channel 3 can be used to manually measure the main battery voltage and channel 9 can be used to measure the voltage of the b ackup battery .
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 146 of 183 ? 2016 dialog semiconductor 18.12 fixed t hreshold n on - adc w arning nirq m ode a comparator with a threshold of vdd_ref (1.2 v ) is connected to the input of channel 5. the comparator is asserted whenever the input voltage is excessing or dropping below 1.2 v for at least 10ms (debouncing) when being enabled via comp1v2_en. a status - flag comp_det is indicating the actual state and a mask able interrupt request e_comp_1v2 is generated at falling and rising edge state transitions. the comparator has to be disabl ed via comp1v2_en when auto measurements with high resolution are executed on adcin5. 18.13 a7: xy t ouch s creen i nterface the tsi operates as a sub - system within the scheduler, using the slots to step through tasks such as; pen down detection, matrix switching a nd settling, and x (one - dimensional resistor network) or xy measurements including pen pressure (z). 18.13.1 features compatible with 4 - wire resistive touch screens and supports pen pressure measurement unidirectional resistor network measurements (xp mode) x+, x - , y+, y - inputs can be alternatively used for multiplexed manual measurements on gp - adc channel 7 pen detection, pen controlled automatic measurements and nirq generation with application wake - up supports configurable low - power schemes includes tsi pre - c harging (to compensate external noise reduction capacitors) and tsi settling to let mechanical vibration of tsi layer sheet stabilize prior to measurement maximum x&y sample rate: 3 khz (pen pressure: 1 khz) figure 52 : tsi s witc h m atrix 18.14 pen d own d etect when ever the screen is touched outside of autonomous tsi sequences (auto_tsi_en is released) the pen detection will issue an interrupt and will trigger a wake up from power - down mode. an autonomous start of configured tsi sequences (xyz or x mode) can be armed in parallel to
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 147 of 183 ? 2016 dialog semiconductor pen_det_en (requires a valid supply voltage at tsiref) ; otherwise the host has to start the tsi measurements by asserting auto_tsi_en. for a single sequence of x&y&z&p (or x&p) the host has to disable auto_tsi_e n when receiving the e_tsi_ready interrupt request. for pen detection the yn switch is closed, grounding the y plate. the xp signal is internally connected by switch pdsw to a current source. when the screen is touched, the formed conducting path steers t he current to ground and a low voltage triggers an interrupt request. when pen detect is blocked the pdsw is opened to isolate the current from the resistor matrix and adc. as long as only the pen detection is running the current source is supplied from vd dcore (2.5 v ). otherwise the supply will be switched to tsiref which should be connected to ldo9 or a similar high precision regulator. 18.15 tsi s cheduler the tsi measurement circuitry is supplied from tsiref. when measuring the x position the x - switch is clos ed (grounding the x plane), the x+ switch is closed (charging the x plane) and later the y+ signal is connected to the adc input for measurement. when measuring the y position the y - switch is closed (grounding the y plane), the y+ switch is closed (chargi ng the y plane) and later the x+ signal is connected to the adc input. the tsi function operates every half - slot of the scheduler, performing automatic x, y, z (and pen detect) measurements of the touch screen resistive potentiometer. the resulting xyp or xyzp (xp) measurements are then available from the distributed tsi_x & tsi_y (and (tsi_z) registers. whenever a xyp or xyzp (or alternatively xp) data block is ready an interrupt is generated to inform the host about new data to be read. the registers latc h the results for all three/four values to ensure an autonomic data read, given that a new measurement may become available whilst reading the multiple registers. filtering of lcd noise is handled by external capacitors connected from each tsi pin to grou nd. a low pass filter is formed with the touch screen resistance that forces a longer settling time prior to adc sampling. the time between switching and measurement conversion is handled by control bits. to reduce power consumption the data block measurement can be made intermittently. the gap between actual measurements specifies a delay in multiples of slot time. a value of zero indicates the xyp, xyzp (or xp) block measurements are continually repeated. otherwise the specified number of slots is skipped in advance to the next xyp, xyzp (or xp) measurement. in summary a settling delay precedes an x measurement, followed by a settling delay preceding a y measurement, which is performed identical to the z and pen detection measurements. a number of slots are missed between a pair of xyp, xyzp (or xp) block meas urements. figure 53 shows an example sequence explaining tsi_delay (2 slots) and tsi_skip (2 slots) in xp mode . figure 53 : examp le s equence i n xp m ode slot automatic tsi measurements go x - x x s w c l o s e d m e a s u r e x t s i _ d e l a y t s i _ s k i p - p - - go x t s i _ d e l a y p s w c l o s e d p e n d e t e c t i o n x s w c l o s e d
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 148 of 183 ? 2016 dialog semiconductor 18.16 pen p ressure when measuring z the x - switch is closed (grounding the x plane), the y+ switch is closed (charging the y plane) and the x+ signal is later then connected to the adc input for measuring the value. the pen pressure can then be estimat ed from the touch resistance pressure which has to be calculated by the host from the measured x, y and z values and the known resistance values of the tsi x - and y - plates (rx and ry). manual measurements can be executed by asserting tsi_man. if asserted i n combination with auto_tsi_en = 1 it forces the immediate single tsi measurement selected within tsi_mode (not waiting for an activate pen detection). if auto_tsi_en = 0 all tsi input channels can be used as further general purpose inputs routed via tsi_m ux to adc channel 7. in combination with the assertion of tsi_sel_0 to tsi_sel_3 this interface mode supports a wide range of host controlled voltage/impedance measurements with adc channel 7. table 55 : registers s ummary name (bits) description auto_tsi_en touch screen block enable. regular measurements of x - y and pen detection are scheduled. pen_det_en enables pen detection mode. tsi_mode 0: xyzp mode (x&y&z plus two x&y measurement, each followed by a pen detection) 1: xp mode (x measurements followed by a pen detection) e_pen_down pen touch detected. set when pen touch down, else reset. flags nirq and wake up with current value shown in status registers. e_tsi_ready interrupt request. cleared by reading event register. m_ts i_ready interrupt request mask. set to 1 to disable interrupt. m_pen_down interrupt request mask. set to 1 to disable interrupt. tsi_xm, tsi_ym, tsi_xl,tsi_yl, tsi_zl, pen_down tsi_z touch screen x, y and z readings: r107: tsi_x bits 9:2 r107+1: tsi_y bits 9:2 r107+2: tsi_x bits 1:0, tsi_y bits 1:0, tsi_z bits 1:0, pen_down r107+3: tsi_z bits 9:2 (used to calculate the pen pressure) to ensure a synchronous data read, the assertion of the tsi_ready event latches the latest x&y (and z) measurements. the v alues at addresses r107, r107+1 & r107+2 (& r107+3 in xyzp mode) can then be safely read until the event was cleared by the host, even if another tsi measurement has occurred in the elapsed time between reads. the addresses are sequential, allowing a 3 or 4 word page mode 2 - wire read. tsi_delay delay between closing x and y switches and adc conversion: 0=0 slot: switches closed only for adc conversion. this allows 6 s for settling. 1=1 slot, 2=2 slots, 3=4 slots switches are set at the end of adc conversion, reading occurs in next slot and the pattern repeats. delay of 1 slot enables continuous x, y, z (and p) readings. tsi_skip delay between two measurements (x&y or x&y&z) where no tc measurements are made (between x values for xp mode). during t his period the switches are open and no current is flowing through the screen so reducing average current consumption. 0 = continuous operation. 1 = 2 slot, 2 = 5 slot, 3 = 10 slot, 4 = 30 slot, 5 = 80 slot, 6 = 130 slot, 7 = 330
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 149 of 183 ? 2016 dialog semiconductor slot. tsi_man when set with auto_tsi_en released, the following registers override the normal operation. tsi_sel_0 tsi_sel_1 tsi_sel_2 tsi_sel_3 direct setting of xy switches: 0 = open x+, 1 = close x+ 0 = open x - , 1 = close x - 0 = open y+, 1 = close y+ 0 = open y - , 1 = close y - tsi_mux direct setting of mux selecting which xy pin is routed to gpadc_in7 input. depending on the mux settings the result will be available either in the tsi_x or tsi_y registers named in brackets: 00 = x+ (tsi_xm, tsi_xl) 01 = y+ (tsi_ym, tsi_yl) 10 = x - (tsi_xm, tsi_xl) 11 = y - (tsi_ym, tsi_yl) adcref adc reference connection. 0 = tsiref/vss 1 = x+/x - , y+/y - or y+/x - depending on the channel being measured (x/y/z) 18.17 gp - adc table 56 : gp - adc c ontrol r egisters register a d dress bit t ype label description r81 adc_man 3:0 r/w mux_sel 0000: vddout pin (channel 0) selected 0001: ich (channel 1) selected 0010: tbat pin (channel 2) selected 0011: vbat pin (channel 3) selected 0100: adcin4 selected 0101: adcin5 selected 0110: adcin6 selected 0111: tsi (channel 7) selected) 1000: internal t - sense using gain 1 (channel 8) selected 1001: vbbat - voltage 4 r/w man_conv perform manual conversion. bit is reset to 0 when conversion is complete. 7:5 r register a d dress bit t ype label description r82 adc_cont 0 r/w auto_vdd_en 0: vddout auto measurements disabled 1: vddout auto measurements enabled 1 r/w auto_ad4_en 0: adcin4 auto measurements disabled 1: adcin4 auto measurements enabled
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 150 of 183 ? 2016 dialog semiconductor 2 r/w auto_ad5_en 0: adcin5 auto measurements disabled 1: adcin5 auto measurements enabled 3 r/w auto_ad6_en 0: adcin6 auto measurements disabled 1: adcin6 auto measurements enabled 4 r/w ad4_isrc_en 0: disable adcin4 15 a current source 1: enable adcin4 15 a current source 5 r/w tbat_isrc_en 0: tbat 50 a current source enabled one slot before measurement (disabled after measurement) 1: enable tbat 50 a current source permanently 6 r/w adc_mode 0: measurement sequence interval 10 ms (economy mode) 1: measurement sequence interval 1 ms (recommended for tsi mode) 7 r/w comp1v2_en 0: disable 1.2 v comparator at adcin5 1: enable 1.2 v comparator register a d dress bit t ype label description r83 adc_res_l 1:0 r adc_res_lsb 10 - bit manual conversion result (2 lsbs) register a d dress bit t ype label description r84 adc_res_h 7:0 r adc_res_msb 10 - bit manual conversion result (8 msbs) register a d dress bit t ype label description r85 vdd_res 7:0 r vddout_res 0x00 C 0xff: auto vddout conversion result (adcin0) 00000000 corresponds to 2.5 v 11111111 corresponds to 4.5 v register a d dress bit t ype label description r86 vdd_mon 7:0 r/w vddout_mon vddout_mon threshold setting (8 - bit). 00000000 corresponds to 2.5 v 11111111 corresponds to 4.5 v register a d dress bit t ype label description r87 ichg_av 7:0 r ichg_av charger current average conversion result, 8 msbs from an internal 18 - bit accumulator, updated every 10.24 s :
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 151 of 183 ? 2016 dialog semiconductor 00000000 corresponds to 0 ma, 11111111 corresponds to 1000 ma register a d dress bit t ype label description r88 ichg_thd 7:0 r/w ichg_thd reduced battery charging current detection threshold (compared with ichg_av) 00000000 corresponds to 0 ma, 11111111 corresponds to 1000 ma register a d dress bit t ype label description r89 ichg_end 7:0 r/w ichg_end battery charging end point current detection threshold (compared with ichg_av) 00000000 corresponds to 0 ma, 11111111 corresponds to 1000 ma register a d dress bit t ype label description r90 tbat_res 7:0 r tbat_res 00000000 C 11111111: auto adc tbat conversion result (adcin1) register a d dress bit t ype label description r91 tbat_highp 7:0 r/w tbat_highp 00000000 C 11111111: tbat high temperature threshold register a d dress bit t ype label description r92 tbat_highn 7:0 r/w tbat_highn 00000000 C 11111111: tbat high temperature resume charging threshold (typically 45 c) register a d dress bit t ype label description r93 tbat_low 7:0 r/w tbat_low 00000000 C 11111111: tbat low temperature threshold (typically 0 c) register a d dress bit t ype label description r94 t_offset 7:0 r/w t_offset 10000000 C 01111111: signed twos complement calibration offset for junction temperature
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 152 of 183 ? 2016 dialog semiconductor measurement register a d dress bit t ype label description r95 adcin4_res 7:0 r adcin4_res 00000000 C 11111111: auto adc adcin4 conversion result register a d dress bit t ype label description r96 auto4_high 7:0 r/w auto4_high 00000000 C 11111111: adcin4 high level threshold register a d dress bit t ype label description r97 auto4_low 7:0 r/w auto4_low 00000000 C 11111111: adcin4 low level threshold register a d dress bit t ype label description r98 adcin5_res 7:0 r adcin5_res 00000000 C 11111111: auto adc adcin5 conversion result register a d dress bit t ype label description r99 auto5_high 7:0 r/w auto5_high 00000000 C 11111111: adcin5 high level threshold register a d dress bit t ype label description r100 auto5_low 7:0 r/w auto5_low 00000000 C 11111111: adcin5 low level threshold register a d dress bit t ype label description r101 adcin6_res 7:0 r adcin6_res 00000000 C 11111111: auto adc adcin6 conversion result register a d dress bit t ype label description r102 auto6_high 7:0 r/w auto6_high 00000000 C 11111111: adcin6 high level threshold
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 153 of 183 ? 2016 dialog semiconductor register a d dress bit t ype label description r103 auto6_low 7:0 r/w auto6_low 00000000 C 11111111: adcin6 low level threshold register a ddress bit t ype label description r104 tjunc_res 7:0 r tjunc_res 00000000 C 11111111: auto tjunc conversion result (adcin8)
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 154 of 183 ? 2016 dialog semiconductor 19 tsi control table 57 : tsi c ontrol r egisters register a ddress bit type label description r105 tsi_cont_a 0 r/w auto_tsi_en 0: auto tsi sequence disabled 1: auto tsi sequence measurements enabled (triggered from pen detection or manual measurement) 1 r/w pen_det_en 0: pen detection (repeating sequences measurement) disabled 1: pen detect circuit (repeating sequences measurement) enabled 2 r/w tsi_mode configures tsi to automatically measure sequence either xp or xyzp (xyp) values 0: xyzp mode: x&y&z plus two x&y measurement, each followed by a pen detection 1: xp mode: x measurements each followed by a pen detection. if pen_detect_en is asserted the sequences will be repeated until pen_down is released otherwise only one sequence is measured 5:3 r/w tsi_skip delay between two measurements of x&y&p or x&y&z&p (or x&p) where no measurements are made. during this period the xy switches are open and no current is flowing through the screen so reducing average current consumption. 000: continuous operation (<=3 khz x&y) 001: 2 slots (<=1.875 khz x&y) 010: 5 slots (<=1.200 khz x&y) 011: 10 slots (<=750 hz x&y) 100: 30 slots (<=300 hz x&y) 101: 80 slots (<=120 hz x&y) 110: 130 slots (<=75 hz x&y) 111: 330 slots (<=30 hz x&y) 7:6 tsi_delay delay between closing xy switches and adc measurement to allow external decoupling capacitors to settle (extends the measurement interval in addition to tsi_skip). 00: 0 slot ( switches closed inside adc conversion slot => 6 s for settling) 01: 1 slots (s witches closed at end of previous slot => 56 s for settling) 10: 2 slots (> 156 s for settling) 11: 4 slots (> 256 s for settling) switches are set at the end of previous tsi conversion, reading occurs in the slot following the specified number of delay slots and the pattern repeats. delay of <= 1 slot provides continuous readings.
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 155 of 183 ? 2016 dialog semiconductor register a ddress bit type label description r106 tsi_cont_b 0 r/w tsi_sel_0 0: x+ switch open 1: x+ switch closed 1 r/w tsi_sel_1 0: x - switch open 1: x - switch closed 2 r/w tsi_sel_2 0: y+ switch open 1: y+ switch closed 3 r/w tsi_sel_3 0: y - switch open 1: y - switch closed 5:4 r/w tsi_mux direct setting of mux selecting which xy pin is routed to adc_in7 input. 00: x+ (results will be stored in tsi_xm) 01: y+ (results will be stored in tsi_ym) 10: x - (results will be stored in tsi_xm) 11: y - (results will be stored in tsi_ym) 6 r/w tsi_man when set, starts manual operation of the tsi measurements: if auto_tsi_en is zero an individual measurement configured by tsi_sel_x and tsi_mux will be performed. if auto_tsi_en was asserted the content from tsi_sel_x and tsi_mux will be ignored and a single measurement sequence configured in tsi_mode will be executed. this bit clears automatically a t the end of the selected measurement. 7 r/w adcref adc reference connection for tsi measurements. 0: tsiref/vss 1: x+/x - , y+/y - or y+/x - (for x, y or z measurements) register a ddress bit type label description r107 tsi_x_msb 7:0 r tsi_xm tsi x measurement result - 8 msbs to ensure a synchronous data read, the act of reading tsi_x_msb, latches the latest x & y measurements. the values can then be safely read, even if another tsi measurement has occurred in the elapsed time between reads. the addre sses are sequential, allowing a page mode read. register a ddress bit type label description r108 tsi_y_msb 7:0 r tsi_ym tsi y measurement result - 8 msbs
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 156 of 183 ? 2016 dialog semiconductor register a ddress bit type label description r109 tsi_lsb 1:0 r tsi_xl tsi x measurement result - 2 lsbs 3:2 r tsi_yl tsi y measurement result - 2 lsbs 5:4 r tsi_zl tsi z measurement result - 2 lsbs 6 r pen_down pen_down state: 0: pen touch not detected 1: pen touch detected 7 r reserved register a ddress bit type label description r110 tsi_z_msb 7:0 r tsi_zm tsi z measurement result - 8 msbs
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 157 of 183 ? 2016 dialog semiconductor 20 rtc calendar and a larm table 58 : rtc c alendar and a larm c ontrol r egisters register a ddress bit type label description r111 count_s 5:0 r/w count_sec 0x00 C 0x3b: rtc seconds read - out. a read of this register latches the current rtc calendar count into the registers r111 to r116 (cohererent for approx 0.5 s ). 6 r/w monitor read - out 0 indicates that the power was lost. read - out of 1 indicates that the clock is ok set to 1 when setting time to arm rtc monitor function. 7 r reserved register a ddress bit type label description r112 count_mi 5:0 r/w count_min 0x00 C 0x3b: rtc minutes read - out 7:6 r reserved register a ddress bit type label description r113 count_h 4:0 r/w count_hour 0x00 C 0x17: rtc hours read - out 7:5 r reserved register a ddress bit type label description r114 count_d 4:0 r/w count_day 0x01 C 0x1f: rtc days read - out 7:5 r reserved register a ddress bit type label description r115 count_mo 3:0 r/w count_month 0x01 C 0x0c: rtc months read - out 7:4 r reserved register a ddress bit type label description r116 5:0 r/w count_year 0x00 C 0x3f: rtc years read - out (0 corresponds to year 2000). a write to this register latches the registers
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 158 of 183 ? 2016 dialog semiconductor count_y r111 to r116 into the current rtc calendar count 7:6 r reserved register a ddress bit type label description r117 alarm_mi 5:0 r/w alarm_min 0x00 C 0x3b: alarm minutes setting 6 r /w alarm_ type alarm event caused by: 0: tick 1: timer alarm 7 r/w tick_ type tick alarm interval is: 0: one second 1: one minute register a ddress bit type label description r118 alarm_h 4:0 r/w alarm_hour 0x00 C 0x17: alarm hours setting 7:5 r reserved register a ddress bit type label description r119 alarm_d 4:0 r/w alarm_day 0x01 C 0x1f: alarm days setting 7:5 r reserved register a ddress bit type label description r120 alarm_mo 3:0 r/w alarm_month 0x01 C 0x0c: alarm months setting 7:4 r reserved register a ddress bit type label description r121 alarm_y 5:0 r/w alarm_year 0x00 C 0x3f: alarm years setting (0 corresponds to year 2000). a write to this register latches the registers r117 to r121 6 r/w alarm_on 0: alarm function is disabled 1: alarm enabled 7 r/w tick_on 0: tick function is disabled 1: periodic tick alarm enabled
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 159 of 183 ? 2016 dialog semiconductor register a ddress bit type label description r122 second_a 7:0 r seconds_a rtc seconds counter a (lsbs). a read of this register latches the current 32 - bit counter into the registers r122 to r125 (cohererent for approx 0.5 s). register a ddress bit type label description r123 second_b 7:0 r seconds_b rtc seconds counter b register a ddress bit type label description r124 second_c 7:0 r seconds_c rtc seconds counter c register a ddress bit type label description r125 second_d 7:0 r seconds_d rtc seconds counter d (msbs)
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 160 of 183 ? 2016 dialog semiconductor 21 register p age 1 table 59 : customer otp re gisters register a ddress bit type label description r128 page_con_p1 6:0 r reserved 7 rw reg_page 0: selects register r1 to r127 1: selects register r129 to r255 register a ddress bit type label description r129 chip_id 3:0 r trc read back of otp trimming release code (trc) C starts with a code 0 7:4 r mrc read back of mask revision code (mrc) C code 0 for aa release register a ddress bit type label description r130 config_id 2:0 r conf_id id for customer variant of start - up voltages and sequencer configuration, written during production of variant 7:3 r customer_id id for customer, written during production of variant
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 161 of 183 ? 2016 dialog semiconductor 22 customer otp register a ddress bit type label description r131 otp_cont 0 r/w otp_transfer 0: no transfer in progress 1: writing 1 to this bit initiates the fusing of selected otp cells with the content from corresponding registers 1: reading 1 indicates the transfer is still ongoing 1 r/w otp_rp 0: transfer is read 1: transfer is programming 2 r/w otp_gp 0: no action 1: transfer includes configuration registers r132 to 0 (plus gp_write_dis and otp_gp_lock ) 3 r/w otp_conf 0: no action 1: transfer includes configuration 0 to 0 (plus otp_conf_lock ) 4 r reserved 5 r otp_gp_lock 0: otp not locked after programming 1: otp will be locked during programming (no further fusing possible) note: write access for fusing only, control state is loaded from otp defaults after por 6 r/w otp_conf_lock 0: otp registers 0 to 0 not locked after programming (only for unmarked evaluation samples) 1: otp re gisters 0 to 0 will be locked during p rogramming (set for all marked parts, no further fusing possible) note: write access for fusing only, control state is loaded from otp defaults after por 7 r/w gp_write_dis 0: enables write access to gp_id registers 1: gp_id registers are read only no te: write access for fusing only, control state is loaded from otp defaults after por register a ddress bit type label description r132 osc_trim 7:0 r/w trim_32k bits for correction of the 32 khz oscillator frequency: 10000000: - 244.1ppm 11111111: - 1.9ppm 00000000: off 00000001: 1.9ppm (1/(32768*16)) 01111111: 242.2ppm
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 162 of 183 ? 2016 dialog semiconductor register a ddress bit type label description r133 gp_id_0 7:0 r/w gp_0 data from fuse array (otp) register a ddress bit type label description r134 gp_id_1 7:0 r/w gp_1 data from fuse array (otp) register a ddress bit type label description r135 gp_id_2 7:0 r/w gp_2 data from fuse array (otp) register a ddress bit type label description r136 gp_id_3 7:0 r/w gp_3 data from fuse array (otp) register a ddress bit type label description r137 gp_id_4 7:0 r/w gp_4 data from fuse array (otp) register a ddress bit type label description r138 gp_id_5 7:0 r/w gp_5 data from fuse array (otp) register a ddress bit type label description r139 gp_id_6 7:0 r/ r/w gp_6 data from fuse array (otp) note write access disabled to gp_id if gp_write_dis fused with 1 .
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 163 of 183 ? 2016 dialog semiconductor register a ddress bit type label description r140 gp_id_7 7:0 r/w gp_7 data from fuse array (otp) register a ddress bit type label description r141 gp_id_8 7:0 r/w gp_8 data from fuse array (otp) register a ddress bit type label description r142 gp_id_9 7:0 r/w gp_9 data from fuse array (otp)
da9053 flexible high - power system pmic with 1.8 a switching usb power manager datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 164 of 183 ? 2016 dialog semiconductor 23 register map 23.1 overview most register bits (exceptions are for example, fault_log or chg_time), that are not loaded from otp are reset to defaults (zero in most cases) when powering up from reset mode . register bits shown in blue are loaded from otp.
da9053 flexible h igh - p ower s ystem pmic with s witching usb p ower m anagement datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 0 0 165 of 183 ? 2016 dialog semiconductor r function 7 6 5 4 3 2 1 0 page 0 system control and event registers (sysmon) ? r0 page_con reg_page reserved ? r1 status_a vdat_det vbus_sel dcin_sel vbus_det dcin_det id_gnd id_float nonkey ? r2 status_b comp_det sequencing gp_fb2 chg_to chg_end chg_lim chg_pre chg_att ? r3 status_c gpi7 gpi6 gpi5 gpi4 gpi3 gpi2 gpi1 gpi0 ? r4 status_d gpi15 gpi14 gpi13 gpi12 gpi11 gpi10 gpi9 gpi8 ? r5 event_a m_comp_1v2 m_seq_rdy e_alarm e_vdd_low e_vbus_rem e_dcin_rem e_vbus_det e_dcin_det ? r6 event_b e_tsi_ready e_pen_down e_adc_eom e_tbat e_chg_end e_id_gnd e_id_float e_nonkey ? r7 event_c e_gpi7 e_gpi6 e_gpi5 e_gpi4 e_gpi3 e_gpi2 e_gpi1 e_gpi0 ? r8 event_d e_gpi15 e_gpi14 e_gpi13 e_gpi12 e_gpi11 e_gpi10 e_gpi9 e_gpi8 ? r9 fault_log wait_shut nsd_shut key_shut reserved temp_over vdd_start vdd_fault twd_error ? r10 irq_mask_a m_comp_1v2 m_seq_rdy m_alarm m_vdd_low m_vbus_rem m_dcin_rem m_vbus_vld m_dcin_vld ? r11 irq_mask_b m_tsi_ready m_pen_down m_adc_eom m_tbat m_chg_end m_id_gnd m_id_float m_nonkey ? r12 irq_mask_c m_gpi7 m_gpi6 m_gpi5 m_gpi4 m_gpi3 m_gpi2 m_gpi1 m_gpi0 ? r13 irq_mask_d m_gpi15 m_gpi14 m_gpi13 m_gpi12 m_gpi11 m_gpi10 m_gpi9 m_gpi8 ? r14 control_a gpi_v pm_o_ type pm_o_v pm_i_v pm_if_v pwr1_en pwr_en sys_en ? r15 control_b shutdown deep_sleep write_mode bbat_en otpread_en auto_boot act_diode buck_merge ? r16 control_c blink_dur blink_frq debouncing pm_fb2_pin pm_fb1_pin ? r17 control_d watchdog acc_det_en gpi14_15_sd nonkey_sd keepact_en twdscale ? r18 pd_dis pm - cont_pd out_32k_pd chg_bbat_pd chg_pd hs - 2 - wire _pd pm - if_pd gp - adc_pd gpio_pd ? r19 interface if_base_addr ncs_pol r/w_pol cpha cpol if_ type ? r20 reset reset_event reset_timer gpio control registers (gpio) ? r21 gpio_0 - 1 gpio1_ mode gpio1_ type gpio1_pin gpio0_ mode gpio0_ type gpio0_pin ? r22 gpio_2 - 3 gpio3_ mode gpio3_ type gpio3_pin gpio2_mode gpio2_ type gpio2_pin ? r23 gpio_4 - 5 gpio5_ mode gpio5_ type gpio5_pin gpio4_ mode gpio4_ type gpio4_pin ? r24 gpio_6 - 7 gpio7_ mode gpio7_ type gpio7_pin gpio6_ mode gpio6_ type gpio6_pin ? r25 gpio_8 - 9 gpio9_ mode gpio9_ type gpio9_pin gpio8_ mode gpio8_ type gpio8_pin ? r26 gpio_10 - 11 gpio11_ mode gpio11_ type gpio11_pin gpio10_ mode gpio10_ type gpio10_pin ? r27 gpio_12 - 13 gpio13_ mode gpio13_ type gpio13_pin gpio12_ mode gpio12_ type gpio12_pin ? r28 gpio_14 - 15 gpio15_ mode gpio15_ type gpio15_pin gpio14_ mode gpio14_ type gpio14_pin power sequencer control registers (seq) ? r29 id_0_1 ldo1_step wait_id_always sys_pre def_supply nres_mode ? r30 id_2_3 ldo3_step ldo2_step ? r31 id_4_5 ldo5_step ldo4_step ? r32 id_6_7 ldo7_step ldo6_step ? r34 id_10_ ldo9_step ldo8_step ? r34 id_10_11 pd_dis_step ldo10_step ? r35 id_12_13 vmem_sw_step vperi_sw_step ? r36 id_14_15 buckpro_step buckcore_step ? r37 id_16_17 buckperi_step buckmem_step
da9053 flexible h igh - p ower s ystem pmic with s witching usb p ower m anagement datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 0 0 166 of 183 ? 2016 dialog semiconductor ? r38 id_18_19 gp_rise2_step gp_rise1_step ? r39 id_20_21 gp_fall2_step gp_fall1_step ? r40 seq_status seq_pointer wait_step ? r41 seq_a power_end system_end ? r42 seq_b part_down max_count ? r43 seq_timer seq_dummy seq_time power supply control registers (reg) ? r44 buck_a bpro_ilim bpro_mode bcore_ilim bcore_mode ? r45 buck_b bperi_ilim bperi_ mode bmem_ilim bmem_ mode ? r46 buckcore bcore_conf bcore_en vbcore ? r47 buckpro bpro_conf bpro_en vbpro ? r48 buckmem bmem_conf bmem_en vbmem ? r49 buckperi bperi_conf bperi_en vbperi ? r50 ldo1 ldo1_conf ldo1_en vldo1 ? r51 ldo2 ldo2_conf ldo2_en vldo2 ? r52 ldo3 ldo3_conf ldo3_en vldo3 ? r53 ldo4 ldo4_conf ldo4_en vldo4 ? r54 ldo5 ldo5_conf ldo5_en vldo5 ? r55 ldo6 ldo6_conf ldo6_en vldo6 ? r56 ldo7 ldo7_conf ldo7_en vldo7 ? r57 ldo8 ldo8_conf ldo8_en vldo8 ? r58 ldo9 ldo9_conf ldo9_en vldo9 ? r59 ldo10 ldo10_conf ldo10_en vldo10 ? r60 supply v_lock vmem_sw_en vperi_sw_en vldo3_go vldo2_go vb_mem_go vb_pro_go vb_core_go ? r61 pulldown reserved reserved ldo5_pd_dis ldo2_pd_dis ldo1_pd_dis mem_pd_dis pro_pd_dis core_pd_dis charging control registers (charge) ? r62 chg_buck chg_temp chg_usb_ilim chg_buck_lp chg_buck_en iset_buck ? r63 wait_cont wait_dir rtc_clock wait_mode en_32kout delay_time ? r64 iset iset_dcin iset_usb ? r65 bat_chg ichg_pre ichg_bat ? r66 chg_cont vchg_bat vch_thr ? r67 input_cont tctr_mode vchg_drop dcin_susp vbus_susp tctr ? r68 chg_time chg_time backup battery charging control registers (bbat) ? r69 bbat_cont bcharger_iset bcharger_vset boost and led driver control registers (led) ? r70 boost e_b_fault m_b_fault boost_frq boost_ilim led3_in_en led2_in_en led1_in_en boost_en ? r71 led_cont sel_led_mode led3_icont led3_ramp led3_en led2_ramp led2_en led1_ramp led1_en ? r72 ledmin ledmin_current ? r73 led1_conf led1_current ? r74 led2_conf led2_current ? r75 led3_conf led3_current ? r76 led1_cont led1_dim led1_pwm ? r77 led2_cont led2_dim led2_pwm ? r78 led3_cont led3_dim led3_pwm
da9053 flexible h igh - p ower s ystem pmic with s witching usb p ower m anagement datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 0 0 167 of 183 ? 2016 dialog semiconductor ? r79 led4_cont led4_dim led4_pwm ? r80 led5_cont led5_dim led5_pwm gp - adc control registers (gpadc) ? r81 adc_man reserved man_conv mux_sel ? r82 adc_cont comp1v2_en adc_mode tbat_isrc_en ad4_isrc_en auto_ad6_en auto_ad5_en auto_ad4_en auto_vdd_en ? r83 adc_res_l reserved adc_res_lsb ? r84 adc_res_h adc_res_msb ? r85 vdd_res vddout_res ? r86 vdd_mon vddout_mon ? r87 ichg_av ichg_av ? r88 ichg_thd ichg_thd ? r89 ichg_end ichg_end ? r90 tbat_res tbat_res ? r91 tbat_highp tbat_highp ? r92 tbat_highn tbat_highn ? r93 tbat_low tbat_low ? r94 t_offset t_offset ? r95 adcin4_res adcin4_res ? r96 auto4_high auto4_high ? r97 auto4_low auto4_low ? r98 adcin5_res adcin5_res ? r99 auto5_high auto5_high ? r100 auto5_low auto5_low ? r101 adcin6_res adcin6_res ? r102 auto6_high auto6_high ? r103 auto6_low auto6_low ? r104 tjunc_res tjunc_res tsi control registers (tsi) ? r105 tsi_cont_a tsi_delay tsi_skip tsi_mode pen_det_en auto_tsi_en ? r106 tsi_cont_b adcref tsi_man tsi_mux tsi_sel_3 tsi_sel_2 tsi_sel_1 tsi_sel_0 ? r107 tsi_x_msb tsi_xm ? r108 tsi_y_msb tsi_ym ? r109 tsi_lsb reserved pen_down tsi_zl tsi_yl tsi_xl ? r110 tsi_z_msb tsi_zm rtc calendar and alarm (rtc) ? r111 count_s reserved monitor count_sec ? r112 count_mi reserved count_min ? r113 count_h reserved count_hour ? r114 count_d reserved count_day ? r115 count_mo reserved count_month ? r116 count_y reserved reserved count_year ? r117 alarm_mi tick_ type alarm_ type alarm_min ? r118 alarm_h reserved alarm_hour ? r119 alarm_d reserved alarm_day ? r120 alarm_mo reserved alarm_month
da9053 flexible h igh - p ower s ystem pmic with s witching usb p ower m anagement datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 0 0 168 of 183 ? 2016 dialog semiconductor ? r121 alarm_y tick_on alarm_on alarm_year ? r122 second_a seconds_a ? r123 second_b seconds_b ? r124 second_c seconds_c ? r125 second_d seconds_d page 1 customer otp (mem) ? r128 page_con reg_page reserved ? r129 chip_id mrc trc ? r130 config_id customer_id conf_id ? r131 otp_cont gp_write_dis otp_conf_lock otp_gp_lock reserved otp_conf otp_gp otp_rp otp_transfer ? r132 osc_trim trim_32k ? r133 gp_id_0 gp_0 ? r134 gp_id_1 gp_1 ? r135 gp_id_2 gp_2 ? r136 gp_id_3 gp_3 ? r137 gp_id_4 gp_4 ? r138 gp_id_5 gp_5 ? r139 gp_id_6 gp_6 ? r140 gp_id_7 gp_7 ? r141 gp_id_8 gp_8 ? r142 gp_id_9 gp_9
da9053 flexible high - power system pmic with switching usb power management datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 169 of 183 ? 2016 dialog semiconductor 24 external c omponent s election 24.1 capacitor s election ceramic capacitors are used as bypass capacitors at all vdd and output rails. when selecting a capacitor, especially for types with high capacitance at smallest physical dimension, the dc bias characteristic has to be taken into account. on the vddout main supply rail a minimum distributed capacitance of 80 f with the following split is recommended: 2x 10 f close to vddout pin 22 f close to vddbuck_peri_pro buck supply pin 22 f close to vddbuck_core buck supply pin 10 f close to vddbuck_mem buck supply pin 4 . 7 f close to boost converter input (coil) 2 x 1 f close to vdd_ldox pins table 60 : recommended c apacitor t ypes application value size temp. char. tolerance rated voltage type vldo1, vldo2, vldo5, vldo9 output bypass 4x 1 f 0402 x5r +/ - 15 % +/ - 10 % 10 v murata grm155r61a105ke15d vldo3, vldo4, vldo6, vldo7, vldo8, vldo10 output bypass 6x 2.2 f 0402 x5r +/ - 15 % +/ - 20 % 6.3 v murata grm155r60j225me15d vddcore output bypass , vref 1x 100 nf 0402 x7r +/ - 15 % +/ - 10 % 16 v murata grm155r71c104ka88d vbuckpro, vbuckperi, vbuckmem output bypass 3x 22 f 0805 x5r +/ - 15 % +/ - 20 % 6.3 v murata grm21br60j226me39l vbuckcore 2x 22 f 0805 x5r +/ - 15 % +/ - 20 % 6.3 v murata grm21br60j226me39l vmem_sw, vcore_sw output bypass 2x 100 nf 0402 x7r +/ - 15 % +/ - 10 % 16 v murata grm155r71c104ka88d vboost output bypass 1x 2.2 f 1206 x7r +/ - 15 % +/ - 10 % 25 v murata grm31mr71e225ka93l vbus, dcin bypass 2x 2.2 f 0603 x5r +/ - 15 % +/ - 10 % 16 v murata grm188r61c225ke15 vbus_prot, dcin_prot bypass 2x 4.7 f 0603 x5r +/ - 15 % +/ - 10 % 6.3 v murata grm188r71j475ke19d
da9053 flexible high - power system pmic with switching usb power management datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 170 of 183 ? 2016 dialog semiconductor application value size temp. char. tolerance rated voltage type vcenter bypass 1x 10 f 0805 x7r +/ - 15% +/ - 10 % 6.3 v murata grm21br70j106ke76l vddout bypass 3x 10 f 0805 x7r +/ - 15% +/ - 10 % 6.3 v murata grm21br70j106ke76l 2x 1 f 0402 x5r +/ - 15% +/ - 10 % 10 v murata grm155r61a105ke15d vbat bypass 1x 10 f 0805 x7r +/ - 15% +/ - 10 % 6.3 v murata grm21br70j106ke76l vdd_ref bypass 1x 2.2 f 1206 x7r +/ - 15% +/ - 10 % 25 v murata grm31mr71e225ka93l xin, xout bypass to vss 2x 12 pf 0402 u2j +/ - 5 % 50 v murata grm1557u1h120jz01d vbbat 1 x 470 nf 0402 x5r +/ - 10% +/ - 10 % 10 v murata grm155r61a474ke15d 24.2 inductor s election inductors should be selected based upon the following parameters: rated max. current: usually a coil provides two current limits, one specifies the maximum current at which the inductance derating due to saturation effects is limited to be within a specified tolerance (typical 20% or 30%) of the peak current. the second limit is defined by the maximum power dissipation and is applied to the effec tive current. dc resistance: critical to converter efficiency and should therefore be minimized. inductance: given by converter electrical characteristics; designed for 2.2 h for all da9053 buck converters, table 61 : recommended inductor t ypes application value size (mm) isat (a) ( note 1 ) irms (a) ( note 2 ) tol (%) dcr ( ? ) type buckcore 1 x 2.2 h 3.7x3.9x1.8 2.55 1. 9 +/ - 20 0.048 toko de3518c 1127as - 2r7m 1 x 2.2 h 4x4x1.2 2.5 1.75 +/ - 30 0.1 coilcraft lps4012 - 222nl 1 x 2.2 h 5x5x1.5 2.7 2 +/ - 20 0.09 coilcraft lps5015 - 222ml buckperi, buckmem, buckpro 3 x 2.2 h 2.5x2x1.2 1.8 1.3 +/ - 20 0.155 tdk vls252012t - 2r2m1r3 3 x 2.2 h 2.5x2x1.2 1.7 1.3 +/ - 20 0.096 toko dfe252012 1239as - h - 2r2n boost 1x 4.7 h 3x3x1.2 1 1.4 +/ - 20 0.13 tdk vls3012t - 4r7m1r0 charger buck 1 x 2.2 h 4x4x1.2 2.5 1.75 +/ - 30 0.1 coilcraft lps4012 - 222nl
da9053 flexible high - power system pmic with switching usb power management datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 171 of 183 ? 2016 dialog semiconductor 1 x 2.2 h 4x4x1.7 2 2.9 +/ - 20 0.07 coilcraft lps4018 - 222ml note 1 value obtained when the nominal value of the inductance has fallen by 30 % under the value at zero current. note 2 value obtained when the temperature has risen by 40 c. this parameter is important for the maximum dc current. 24.3 resistors table 62 : recommended r esistor t ypes application value size tolerance p max type boost current sense 100 m ? 0402 +/ - 2 % 125 mw panasonic erj2bsgr10x iref bias current reference 200 k ? 0402 +/ - 1 % 100 mw panasonic erj2rkf2003x 24.4 external p ass t ransistors and schottky d iodes table 63 : recommended schottky diode and t ransistor t ypes application package type boost fet + schottky wdfn6 2x2x0.8 mm on semiconductor ntljf4156n schottky sod323 bat760 vbus overvoltage protection fet sot - 23 csd25301w1015, pmv65xp dcin overvoltage protection fet sot - 23 csd25301w1015, pmv65xp vbus/dcin dual overvoltage protection fet powerpak1212 - 8 3.3x3.3x1 mm vishay siliconix si7911dn system load switch (active diode) fet sot - 23 3x2.6x1 mm vishay siliconix si2333ds 24.5 backup b attery the backup battery charger supports lithium coin cells as well as supercaps/goldcaps. however if the internal rtc clock is used, the batterys nominal voltage should be above 3 v to allow reasonable backup times though the backup battery charger allows charge voltages from 1.1 v to 3.1 v ( for example, for externa l rtc clock modules). table 64 : example b ackup b attery t ypes type size manufacturer lithium battery (rechargeable) ml414, 1.0 mah, 3.1 v 4.8 (dia.) x 1.4 mm sanyo, panasonic electric double layer capacitor (gold capacitor) eecen0f 204xx, 0.2 f, 3.3 v 6.8 (dia.) x 1.8 mm panasonic electric double layer capacitor (gold capacitor) eecep0e333a, 0.033 f, 2.6 v 3.8 (dia.) x 1.5 mm panasonic
da9053 flexible high - power system pmic with switching usb power management datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 172 of 183 ? 2016 dialog semiconductor 24.6 battery p ack t emperature s ensor (ntc) in order to achieve reasonable accuracy over the relevant temperature range ( for example, 0 c to 50 c for charging) by using the internal 50 a current source, the recommended ntc should have a nominal resistance of 10 k ? (25) and its resistance should not exceed 50 k ? within this range. table 65 : example b attery p ack t emperature s ensor type size manufacturer ncp15xh103j03rc 0402 murata 24.7 crystal the real time clock mod ule requires an external 32.768 khz crystal. for crystal selection the effective load capacitance has to be taken into account. it includes both external capacitors on pins xin and xout in series combination and the pcb and da9053 stray capacitances. for e xample, if two times 12pf external capacitors are used, which gives a series combination of 6pf, and the stray capacitance is 3pf, and then the crystal type specified for a load capacitance of 9pf should be chosen. different stray capacitances may require different external capacitors and/ or a different crystal type. furthermore the series resistance of the crystal must not exceed 100 k ? . table 66 : recommended c rystal t ype type size manufacturer cc7v - t1a 32.768 khz 9.0 pf +/ - 30 ppm 3.2x1.5x0.9 mm micro crystal
da9053 flexible high - power system pmic with switching usb power management datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 173 of 183 ? 2016 dialog semiconductor 25 layout g uidelines 25.1 general r ecommendations appropriate trace width and amount of vias should be used for all power supply paths. too high trace resistances can prevent the system from proper operation, for example efficiency and current ratings of switch m ode converters and charger might be degraded. furthermore the pcb might be exposed to thermal hot spots, which can lead to critical overheating due to the positive temperature coefficient of copper. special care must be taken to the da9053 pad connections. the traces of the outer row should be connected with the same width as the pads and should become wider as soon as possible. for supply pins in the second row connection in an inner layer is recommended (depending on the maximum current two or more vias m ight be required). a common ground plane should be used, which allows proper electrical and thermal performance. noise sensitive references like the vref capacitor and iref resistor should be referred to a silent ground which is connected at a star point underneath or close to the da9053 main ground connection. generally all power tracks with discontinuous and / or high currents should be kept as short as possible. noise sensitive analogue signals like feedback lines or crystal connections should be kept a way from traces carrying pulsed analogue or digital signals. this can be achieved by separation (distance) or shielding with quiet signals or ground traces. see dialog semiconductor applications note an - pm - 010_pcb_layout_guidlines.pdf for further layout gu idance. 25.2 system s upply and c harger trace resistance of the vbusprot (or dcin_prot) bypass capacitor to vcenter has to be minimized to allow proper operation of the charge and system current control. in case an external pmos transistor is used to bypass the internal active diode, its connection trace resistance has to be kept to a minimum. the placement of the distributed capacitors at vddout must ensure that all vdd inputs, especially to the buck converters and ldos, are connected to a bypass capacitor close to the pads. it is recommended to place at least two 1 f capacitors close to the ldo supply pads and at least one 10 f close to the buck vdd rail. using a local power plane underneath the chip for vddout might be considered. adequate heat sink areas sho uld be used for at least one terminal of the external overvoltage protection and / or active diode fets. 25.3 ldos and s witched m ode s upplies transient current loops area of the switched mode converters should be minimized. the common references (vref capacitor , iref resistor) should be placed close to da9053, cross coupling to any noisy digital or analog trace must be avoided. output capacitors of the ldos should be placed close to the output pins. small capacitors ( for example 100 nf) are also required close t o the input pins of the supplied devices. care must be taken that no current is carried on feedback lines (buck output voltages vbuckxx and boost current sense inputs (boost_sense_p/n).
da9053 flexible high - power system pmic with switching usb power management datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 174 of 183 ? 2016 dialog semiconductor 25.4 crystal o scillator the crystal and its load capacitors should be placed as close as possible to the ic with short and symmetric traces. the traces must be isolated from noisy signals, especially from clocked digital ones. ideally the lines are buried between two ground laye rs, surrounded by additional ground traces. 25.5 t hermal c onnection, l and p ad and s tencil d esign the da9053 provides a centre ground plane, which is soldered directly to the pcbs centre ground pad. this pcb ground pad must be connected with as many vias and as direct as possible to the pcbs main ground plane in order to achieve good thermal performance. solder mask openings for the ground pad must be split by following a certain pattern like stripes or round shapes or squares, as a solid square would apply too much solder paste and the signal pads might not be connected properly. as da9053 also provides different sizes of the signal pads, some adaptation of the mask openings might be required as well (generally small pads a bit larger, large pads a bit smaller than the pad itself). vias inside or next to the pads should be filled. an appropriately fine solder paste is required.
da9053 flexible high - power system pmic with switching usb power management datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 175 of 183 ? 2016 dialog semiconductor 26 definitions 26.1 power d issipation and t hermal d esign when designing with the da9053 consideration must be given to power dissipation a s the level of integration of the device can result in high power dissipation when all functions are operating with high battery voltages. exceeding the package power dissipation will result in the internal thermal sensor shutting down the device until it has cooled sufficiently. the package includes thermal management paddle to enable improved heat spreading on the pcb. linear regulators operating with a high current and high differential voltage between input and output will dissipate the following power for e xample : a regulator supplying 150 ma @ 2.8 v from a fully charged lithium battery (vdd = 4.1 v) pdiss = (4.1 v - 2.8 v)*0.15 a = 195 mw for switching regulators : pout = pin*efficiency therefore : pdiss = pin - pout example C an 85 % efficient buck converter supplying 1.2 v@ 400 ma as the da9053 is a multiple regulator configuration each supply must be considered and summed to give the total device dissipation (current drawn from the reference and control circuitry can be considered negligible in these calculations). p diss = (v in - v out )*i out p diss = p out - p out efficiency p diss = p out * efficiency 1 - 1 p diss = i out * v out * efficiency 1 - 1 p diss = 1.2v * 0.4a * - 1 1 0.85 = 85mw
da9053 flexible high - power system pmic with switching usb power management datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 176 of 183 ? 2016 dialog semiconductor 27 regulator p arameter s 27.1 dropout v oltage in the da9053 a regulators dropout voltage is defined as the minimum voltage differential between the input and output voltages whilst regulation still takes place. within the regul ator, voltage control takes place across a pmos pass transistor and when entering the dropout condition the transistor is fully turned on and therefore cannot provide any further voltage control. when the transistor is fully turned on the output voltage tr acks the input voltage and regulation ceases. as the da9053 is a cmos device and uses a pmos pass transistor, the dropout voltage is directly related to the on resistance of the device. in the device the pass transistors are sized to provide the optimum ba lance between required performance and silicon area. by employing a 0.25 m process dialog are able to achieve very small pass transistor sizes for superior performance. vdropout=vin C vout = rdson * iout when defining dropout voltage it is specified in relation to a minimum acceptable change in output voltage. for example all dialog regulators have dropout voltage defined as the point at which the output voltage drops 10 mv below the output voltage at the minimum guaranteed operating voltage. the worst c ase conditions for dropout are high temperature (highest on resistance for internal device) and maximum current load. 27.2 power s upply r ejection power supply rejection (psrr) is especially important in the supplies to the rf and audio parts of the telephone. i n a tdma system such as gsm, the 217 hz transmit burst from the power amplifier results in significant current pulses being drawn from the battery. these can peak at up to 2 a before reaching a steady state of 1.4 a (see below). due to the battery having a finite internal resistance (typically 0.5 ? ) these current peaks induce ripple on the battery voltage of up to 500 mv. as the supplies to the audio and rf are derived from this supply it is essential that this ripple is removed otherwise it would show as a 217 hz tone in the audio and could also affect the transmit signal. power supply rejection should always be specified under worst case conditions when the battery is at its minimum operating voltage, when there is minimum headroom available due to dropou t. 27.3 line r egulation static line regulation is a measurement that indicates a change in the regulator output voltage ? vreg (regulator operating with a constant load current) in response to a change in the input voltage ? vin. transient line regulation is a me asurement of the peak change ? vreg in regulated voltage seen when the line input voltage changes.
da9053 flexible high - power system pmic with switching usb power management datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 177 of 183 ? 2016 dialog semiconductor figure 54 : transient and s tatic l ine r egulation 27.4 load r egulation static load regulation is a measurement that indicates a change in the regulator output voltage ?vreg in response to a change in the regulator loading ?load whilst the regulator input voltage remains constant. transient load regulation is a measurement of the peak change in regulated voltage ?vreg seen w hen the regulator load changes. figure 55 : transient and s tatic l oad r egulation 4.6ms tdma frame rate ? v r e g s t a t i c ? v i n ? v r e g t r a n s i e n t 5 7 7 s v bat v reg ? v r e g s t a t i c ? v r e g t r a n s i e n t v reg i load max i load min
da9053 flexible high - power system pmic with switching usb power management datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 178 of 183 ? 2016 dialog semiconductor 28 dialog semiconductor 7 x7 da9053 reference b oard b ill of m aterials 28.1 dialog reference board component i dentification for bill of m aterials qty reference part name value package manufacturer order number 4 c13 ,c20,c21,c32 capcy_0402_new 100n 0402 murata grm155r71c104ka88d 2 c34 ,c35 capcy_0402_new 12p 0402 murata grm155c1h120jz01d 6 c1,c2,c3,c4,c7,c11 capcy_0402_new 1u 0402 murata grm155r61a105ke15 7 c5,c6,c8,c9,c10,c12,c33 capcy_0402_new 2u2 0402 murata grm155r60j225me15 1 c31 capcy_0402_new 470n 0402 murata grm155r61a474ke15d 3 c22,c23,c25 capcy_0603_new 22u 0603 murata grm188r60j226me69 1 c17 capcy_0603_new 10u 0603 murata grm188r60j106m 5 c14 ,c26-c29 capcy_0603_new 4u7 0603 murata grm188r60j475ke19 2 c18,c19 capcy_0805_new 22u 0805 murata grm21br60j226me39l 4 c30,c36,c37,c38 capcy_0805_new 10u 0805 murata grm21br61c106ke15 1 c24 capcy_0805_new 47u 0805 murata grm21bc80e476me15l 1 c39 capcy_0805_new n.c. 0805 murata grm21bc80g226me39l 1 c15 capcy_1206_new 2u2 1206 murata grm31cr71h225ka88 1 l1 indy-inductor_2-4mm 4u7h nr4018t4r7m taiyo yuden nr4018t4r7m 1 l2 inductor_vls3012 2u2h nr3015t2r2m taiyo yuden nr3015t2r2m 1 l3 inductor_vls3012 2u2h nr3015t2r2m taiyo yuden nr3015t2r2m 1 l4 indy-inductor_2-4mm 2u2h nr4018t2r2m taiyo yuden nr4018t2r2m 1 l5 inductor_vls3012 2u2h nr3015t2r2m taiyo yuden nr3015t2r2m 1 l6 indy-inductor_2-4mm 2u2h nr4018t2r2m taiyo yuden nr4018t2r2m 1 r1 resy_0402_new 1m 1 r2 resy_0402_new 68k 1 r3 resy_0402_new 0r1 2 var1,var2 resy_0402 n.c. 0402 avr-m1005c080m 1 r6 resy_0402_new 200k 1% 2 r7,r8 resy_0402_new 100k 1 t1 trafny_ntljf4156n fdfma3n109 mlp6 fairchild farnell order no.1324787 1 t2,t3 trafpy_cds25301w1015 csd25301w1015 wlcsp1x1.5 ti csd25301w1015 1 t4 trafpy_si2333ds_sot23 si2333cds sot-23 fairchild fdv302p 1 x1 xtay_cc7v-t1a 32,768khz 3,2 x 1,5mm micro crystal cc7va-t1a 1 u1 pmcy_kangarooplus da9053 169 ball bga 0.5mm pitch supplied by dialog. 2 j1,j2 15x2 header header 1 c16 capcy_0402_new n.c. 1 d16 dioscy_bat760_sod323 bat760 sod323 nxp rs
da9053 flexible high - power system pmic with switching usb power management datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 179 of 183 ? 2016 dialog semiconductor figure 56 : dialog da9053 r eference b oard
da9053 flexible high - power system pmic with switching usb power management datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 180 of 183 ? 2016 dialog semiconductor 29 packa ge i nformation 29.1 package o utlines figure 57 : 169ld - vfbga (7 x 7 mm) p ackage o utline d rawing
da9053 flexible high - power system pmic with switching usb power management datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 181 of 183 ? 2016 dialog semiconductor figure 58 : 169 - vfbga (11 x 11 mm) p ackage d rawing 30 ordering i nformation the ordering number consists of the part number followed by a suffix indicating the packing method. for details and availability, please consult dialog semiconductor s customer portal or your local sales representative. table 67 : ordering i nformation part nu mber package shipment f orm pack q ua ntity da9053 - xx c51 7 x 7 169 bump bga pb - free/green tray 260 da9053 - xx c52 7 x 7 169 bump bga pb - free/green t&r 3,000 da9053 - xx ha1 11 x 11 169 bump bga pb - free/green tray 168 da9053 - xx ha2 11 x 11 169 bump bga pb - free/green t&r 2000 aec q100 grade 3 da9053 - xx ha1 - a 11 x 11 169 bump bga pb - free/green tray 168 da9053 - xx ha2 - a 11 x 11 169 bump bga pb - free/green t&r 2000 30.1 variants o rdering i nformation da9053 supports delivery of customised variants indicated by xx in the p art number above, please contact your local dialog semiconductor office or representative to discuss requirements.
da9053 flexible high - power system pmic with switching usb power management datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 182 of 183 ? 2016 dialog semiconductor revision h istory revision date description 1.0 01 - jun - 2010 > initial version. 2. 0 17 - oct - 2013 - minor updates 2.1 30 - aug - 2016 - updated to latest template and cosmetic changes
da9053 flexible high - power system pmic with switching usb power management datasheet revision 2.1 31 - aug - 2016 cfr0011 - 120 - 00 183 of 183 ? 2016 dialog semiconductor status definitions revision datasheet status product status definition 1. target development this datasheet contains the design specifications for product development. specifications may be changed in any manner without notice. 2. preliminary qualification this datasheet contains the specifications and preliminary characterization data for products in pre - production. specifications may be changed at any time without notice in order to improve the design. 3. final production this datasheet contains the final specifications for products in volume production. the specifications may be changed at any time in order to improve the design, manufacturing and supply. major specification changes are communicated via customer product no tifications. datasheet changes are communicated via www.dialog - semiconductor.com . 4. obsolete archived this datasheet contains the specifications for discontinued products. the information is provi ded for reference only. disclaimer information in this document is believed to be accurate and reliable. however, dialog semiconductor does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information. dialog semiconductor furthermore takes no responsibility whatsoever for the content in this document if provided by any information source outside of dialog semiconductor. dialog semicond uctor reserves the right to change without notice the information published in this document, including without limitation the specification and the design of the related semiconductor products, software and applications. applications, software, and semic onductor products described in this document are for illustrative purposes only. dialog semiconductor makes no representation or warranty that such applications, software and semiconductor products will be suitable for the specified use without further tes ting or modification. unless otherwise agreed in writing, such testing or modification is the sole responsibility of the customer and dialog semiconductor excludes all liability in this respect. customer notes that nothing in this document may be construe d as a license for customer to use the dialog semiconductor products, software and applications referred to in this document. such license must be separately sought by customer with dialog semiconductor. all use of dialog semiconductor products, software a nd applications referred to in this document are subject to dialog semiconductors standard terms and conditions of sale , available on the company website ( www.dialog - semiconductor.com ) unless otherwise stated. dialog and the dialog logo are trademarks of dialog semiconductor plc or its subsidiaries. all other product or service names are the property of their respective own ers. ? 2016 dialog semiconductor. all rights reserved. rohs compliance dialog semiconductors suppliers certify that its products are in compliance with the requirements of directive 2011/65/eu of the european parliament on the restriction of the use of certain hazardous substances in electrical and electronic equipment. rohs certificates from our suppliers are available on request. contacting dialog semiconductor united kingdom (headquarters) dialog semiconductor (uk) ltd phone: +44 1793 757700 germany dialog semiconductor gmbh phone: +49 7021 805 - 0 the netherlands dialog semiconductor b.v. phone: +31 73 640 8822 north america dialog semiconductor inc. phone: +1 408 845 8500 japan dialog semiconductor k. k. phone: +81 3 5425 4567 taiwan dialog semiconductor taiwan phone: +886 281 786 222 singapore dialog semiconductor singapore phone: +65 64 8499 29 hong kong dialog semiconductor hong kong phone: +852 3769 5200 korea dialog semiconductor korea phone: +82 2 3469 8200 china (shenzhen) dialog semiconductor china phone: +86 755 2981 3669 china (shanghai) dialog semiconductor china phone: +86 21 5424 9058 email: enquiry@diasemi.com web site: www.dialog - semiconductor.com

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